Journal of Xidian University ›› 2020, Vol. 47 ›› Issue (4): 64-69.doi: 10.19665/j.issn1001-2400.2020.04.009

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High-level synthesis design flow for power side-channel security

ZHANG Lu(),MU Dejun,HU Wei,TAI Yu   

  1. School of Cybersecurity, Northwestern Polytechnical University, Xi’an 710072, China
  • Received:2019-12-31 Online:2020-08-20 Published:2020-08-14


The lack of efficient security guidance is a prominent problem in the design flow of high-level synthesis. To tackle this issue, this paper proposes a security-based high-level synthesis design flow featuring the power side-channel vulnerabilities. The side-channel leakage is quantified by establishing a secure component module library, a more efficient and secure parallel scheduling mechanism is generated by optimizing the control flow, and a more secure architecture of the storage system is achieved by optimizing the data flow. The goal is to perform tradeoffs between performance and security, reducing the side-channel risks at the early stage of design and simultaneously generating more secure and efficient cryptographic cores in hardware. Furthermore, the proposed HLS design flow is verified on a field programmable gate array platform. Experimental results show that, in comparison with the traditional design flow, this method reduces the resources by 72% and the clock cycles by 70% and increases the throughput by 88%, and that it can lower the power side-channel risks within an ongoing design to the greatest extent.

Key words: high-level synthesis, hardware design, cypher device, information leakage, power side-channel

CLC Number: 

  • TP393.083