基于Winograd算法的可重构卷积神经网络加速器

doi:10.16180/j.cnki.issn1007-7820.2022.12.005

摘要/Abstract

摘要：

神经网络被广泛应用于模式识别、预测分析、数据拟合等方面,是人工智能的重要基础。神经网络卷积计算量大且网络参数量多,导致了计算时间长且数据访存压力大等问题。针对以上问题,文中基于Winograd算法对卷积计算进行加速,设计了优化的硬件计算结构,提高了数据的复用效率和计算并行度。相较于滑窗卷积,文中所提加速器的计算效率提升了4.352倍。在卷积核梯度计算方面,该加速器采用优化的数据分配方式,减少了数据搬移且满足了多个PE并行计算的数据需求,与CPU相比性能提升了23倍。实验表明,该加速器在VGG-9网络模型下的卷积计算吞吐率可达192.55 GFLOPS,在训练后对CIFAR-10数据集的识别率为76.54%。

关键词: CNN硬件加速器, Winograd, FPGA, 可重构, 卷积加速, 多路并行, 图像识别, VGG网络

Abstract:

Neural network is widely used in pattern recognition, predictive analysis, data fitting and other aspects, and it is an important foundation of artificial intelligence. Due to the large calculation amount of convolution and the large amount of network parameters, neural networks have caused problems such as long calculation time and high data access pressure. In response to the above problems, this study accelerates the convolution calculation based on the Winograd algorithm, designs an optimized hardware calculation structure, which improves the data reuse efficiency and calculation parallelism. Compared with the sliding window convolution, this accelerator increases the calculation efficiency by 4.352 times. In terms of convolution kernel gradient calculation, this accelerator adopts an optimized data distribution method, which reduces data movement and meets the data requirements of multiple PE parallel calculations. Compared with the CPU, the performance is improved by 23 times. Experiments show that the convolution calculation throughput rate of the accelerator can reach 192.55 GFLOPS under the VGG-9 network model, and the recognition rate of the CIFAR-10 data set after training is 76.54%.

Key words: CNN hardware accelerator, Winograd, FPGA, reconfigurable, convolution acceleration, multiplexed parallelism, image identification, VGG network

中图分类号:

TN47

袁子昂,倪伟,冉敬楠. 基于Winograd算法的可重构卷积神经网络加速器[J]. 电子科技, 2022, 35(12): 35-42.

YUAN Ziang,NI Wei,RAN Jingnan. Reconfigurable Convolutional Neural Network Accelerator Based on Winograd Algorithm[J]. Electronic Science and Technology, 2022, 35(12): 35-42.

图/表 17

图1

表1

推理训练公式"

	推理	训练
全连接层	Z^l=W^lX^l+B^l O^l=σ(Z^l)	s^l= $(W l + 1) T$ δ^l⁺¹ δ^l=s^l☉σ'(Z^l) W^l=W^l+αδ^l $(X l) T$ B^l=B^l+αδ^l
	推理	训练
池化层	O^l=maxpool(X^l) O^l=meanpool(X^l)	δ^l=upsample(δ^l⁺¹)
卷积层	Z^l=X^l×K^l+B^l O^l=σ(Z^l)	s^l=δ^l⁺¹×rot180(W^l⁺¹) δ^l=s^l☉σ'(Z^l) K^l=K^l+αδ^l×X^l B^l=B^l+α∑δ^l

表1

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表2

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	文献[17]	文献[18]	文献[19]	本文
网络架构	VGG-16	VGG-16	VGG-16	VGG-9
FPGA芯片	Stratix V	Intel QPI FPGA	Zynq XC7Z045	Virtex6 240T
频率	120 MHz	200 MHz	150 MHz	130 MHz
吞吐率^[16]	117.8 GOPS	124.0 GFLOPS	137.0 GOPS	192.0 GFLOPS
DSP	727	224	780	508
吞吐率/Dsp	0.162	0.553	0.175	0.378

片上资源	已使用/总量	使用率
Slice Registers	93 446/301 440	31%
Slice LUTs	63 302/150 720	42%
Memory	42 048/58 400	72%
DSP48E1s	508/768	66%