隔离驱动芯片高速编解码电路设计

doi:10.16180/j.cnki.issn1007-7820.2025.02.011

电子科技 ›› 2025, Vol. 38 ›› Issue (2): 84-92.doi: 10.16180/j.cnki.issn1007-7820.2025.02.011

隔离驱动芯片高速编解码电路设计

熊张良¹(), 陈苏婷¹, 宣志斌², 赵庭晨², 刘甲俊¹, 傅僈喃¹

1.南京信息工程大学电子与信息工程学院,江苏南京 210044
2.中国电子科技集团公司第五十八研究所,江苏无锡 214000

收稿日期:2023-08-13 修回日期:2023-09-04 出版日期:2025-02-15 发布日期:2025-01-16
通讯作者: 熊张良(1998-),男, E-mail:2799079459@qq.com,硕士研究生。研究方向:磁耦合隔离驱动芯片。 E-mail:2799079459@qq.com
作者简介:陈苏婷(1980-),女,博士,教授。研究方向:人工智能、大数据、嵌入式开发。
宣志斌(1983-),男,高级工程师。研究方向:模拟IC设计。
基金资助:
国家自然科学基金(62272234)

Design of High Speed Encoding and Decoding Circuit for Isolation Driver Chip

XIONG Zhangliang¹(), CHEN Suting¹, XUAN Zhibin², ZHAO Tingchen², LIU Jiajun¹, FU Mannan¹

1. School of Electronics and Information Engineering,Nanjing University of Information Science and Technology, Nanjing 210044,China
2. The 58th Research Institute,China Electronics Technology Group Corporation, Wuxi 214000,China

Received:2023-08-13 Revised:2023-09-04 Online:2025-02-15 Published:2025-01-16
Supported by:
National Natural Science Foundation of China(62272234)

摘要/Abstract

摘要：

文中利用层叠式微型片上变压器的隔离传输方式设计了一种应用于隔离驱动电路的数字隔离器编解码方案。针对现有隔离器主流编解码方案中射频调制功耗过高和脉冲调制速率限制及可靠性问题,文中采用单双脉冲编解码技术降低功耗并优化编解码方式。相较于传统单双脉冲解码方式,将解码电路中采样脉冲信号改为边沿触发信号可提高可靠性,信号传输速率提升近两倍,降低了延时时间,并可结合刷新计时电路和看门狗电路实现数字隔离器的可靠传输。实验结果表明,在新设计下,数字信号可实现DC~90 Mbit·s^-1的隔离传输,编解码整体静态功耗为0.574 mA,动态功耗为0.257 mA·(Mbit·s^-1)^-1,延时时间小于18 ns,脉宽失真小于2 ns。

关键词: 片上变压器, 数字隔离器, 编解码, 脉冲调制, 高速率, 低延时, 高可靠性, 低功耗

Abstract:

A digital isolator encoding and decoding scheme for isolation drive circuits is designed using the isolation transmission method of stacked micro on-chip transformers. In view of the high radio frequency modulation power consumption, pulse modulation rate limitations, and reliability issues in existing isolator mainstream encoding and decoding schemes, single and double pulse encoding and decoding technology is adopted to reduce power consumption and optimize encoding and decoding methods in this study. Compared with traditional single and double pulse decoding methods, replacing the sampled pulse signal in the decoding circuit with an edge triggered signal improves reliability, increases signal transmission rate by nearly twice, reduces delay time, and combines refresh timing circuit and watchdog circuit to achieve reliable transmission of digital isolators. The experimental results show that the digital signal achieves isolated transmission of DC~90 Mbit·s^-1. The overall static power consumption of encoding and decoding is 0.574 mA, the dynamic power consumption is 0.257 mA·(Mbit·s^-1)^-1, the delay time is less than 18 ns, and the pulse width distortion is less than 2 ns.

Key words: on chip transformer, digital isolator, encoding and decoding, pulse modulation, high speed, low latency, high reliability, low power consumption

中图分类号:

TN432

熊张良, 陈苏婷, 宣志斌, 赵庭晨, 刘甲俊, 傅僈喃. 隔离驱动芯片高速编解码电路设计[J]. 电子科技, 2025, 38(2): 84-92.

XIONG Zhangliang, CHEN Suting, XUAN Zhibin, ZHAO Tingchen, LIU Jiajun, FU Mannan. Design of High Speed Encoding and Decoding Circuit for Isolation Driver Chip[J]. Electronic Science and Technology, 2025, 38(2): 84-92.

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参考文献 17

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编码侧	功耗/μA	解码侧	功耗/μA
偏置电路	124.3	偏置电路	125.9
欠压锁定	31.2	欠压锁定	43.1
上电复位	43.6	上电复位	38.5
1 μs计时电路	62.4	5 μs计时电路	11.3
其他	58.5	其他	35.7
总计	320.0	总计	254.5

参数	最小值	典型值	最大值	传输速率/Mbit·s^-1
IDD₁	0.16	0.21	0.28	1
IDD₂	0.05	0.08	0.12	1
IDD₁	1.98	2.12	2.36	10
IDD₂	0.43	0.51	0.61	10
IDD₁	10.87	11.36	12.07	50
IDD₂	2.09	2.28	2.31	50
IDD₁	19.52	19.87	20.55	90
IDD₂	3.86	4.13	4.43	90

参数	文献[7]	文献[14]	本文
工艺/μm	0.500	0.18	0.250
传播延时/ns	20.000	50.00	18.000
最大速率/Mbit·s^-1	40.000	30.00	90.000
脉宽失真/ns	<3	<3	<2
静态功耗/mA	0.570	2.50	0.574
动态功耗/mA·(Mbit·s^-1)^-1	0.213	0.70	0.257

隔离驱动芯片高速编解码电路设计

Design of High Speed Encoding and Decoding Circuit for Isolation Driver Chip

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