电子科技 ›› 2025, Vol. 38 ›› Issue (3): 75-81.doi: 10.16180/j.cnki.issn1007-7820.2025.03.010

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应用于Flash型FPGA的正高压电荷泵

江少祥1(), 禹胜林1, 马金龙2, 吴楚彬2   

  1. 1.南京信息工程大学 电子与信息工程学院,江苏 南京 210000
    2.中国电子科技集团第五十八研究所,江苏 无锡 214000
  • 收稿日期:2023-09-20 修回日期:2023-10-15 出版日期:2025-03-15 发布日期:2025-03-11
  • 通讯作者: 江少祥(2002-),男,E-mail:leslie092013@163.com,硕士研究生。研究方向:Flash型FPGA配置电路设计。
  • 作者简介:禹胜林(1967-),男,博士,教授。研究方向:集成电路封装技术、传感芯片集成感知技术。
  • 基金资助:
    国家自然科学基金(62272234)

Positive High Voltage Charge Pump Applied to Flash-Based FPGA

JIANG Shaoxiang1(), YU Shenglin1, MA Jinlong2, WU Chubin2   

  1. 1. School of Electronics and Information Engineering,Nanjing University of Information Science and Technology,Nanjing 210000,China
    2. The 58th Research Institute of China Electronics Technology Group,Wuxi 214000,China
  • Received:2023-09-20 Revised:2023-10-15 Online:2025-03-15 Published:2025-03-11
  • Supported by:
    National Natural Science Foundation of China(62272234)

摘要:

Flash型FPGA(Filed Programmable Gate Array)在进行编程操作时,电荷泵为编程管栅端提供正高压。为满足Flash型FPGA的上电及时运行性和编程稳定性,要求电荷泵不仅能输出高压,还应具有较快的启动速度和较小的输出电压纹波。文中基于传统交叉耦合电荷泵提出一种正高压电荷泵。电荷泵的主体采取并联双支路结构,降低了输出电压纹波,采用六相不交叠时钟和新增时钟升压模块对电荷泵进行时序控制,在消除了反向电流影响的同时提高了电荷泵启动速度。在输出端设置稳压模块进行稳压调节,保证编程稳定性。仿真结果表明,在电源电压为3.3 V、时钟频率为20 MHz、负载电容为50 pF的条件下,电荷泵启动时间为6.6 μs,输出电压稳定到15 V,输出纹波仅有23 mV。采用0.18 μm CMOS(Complementary Metal Oxide Semiconductor)工艺流片后,测试结果满足Flash型FPGA的编程需求。

关键词: Flash型FPGA, 编程, 高压, 交叉耦合, 并联双支路, 六相不交叠时钟, 纹波, 电荷泵

Abstract:

When Flash-based FPGA(Filed Programmable Gate Array) performs programming operations, the charge pump provides positive high voltage to the gate end of the programming tube. In order to meet the power on timely operation, and programming stability of Flash-based FPGA, the charge pump is required not only be able to output high voltage, but also have fast startup speed and small output voltage ripple. This study proposes a positive high-voltage charge pump based on the traditional cross coupled charge pump. The main body of the charge pump adopts a parallel dual branch structure, reducing the output voltage ripple. It uses a six phase non overlapping clock and a new clock boost module to control the timing of the charge pump, eliminating the impact of reverse current and improving the start speed of the charge pump. A voltage stabilizing module is set at the output end for voltage regulation, ensuring programming stability. The simulation results show that under the conditions of 3.3 V supply voltage, 20 MHz clock frequency and 50 pF load capacitance, the charge pump startup time is 6.6 μs, the output voltage is stable to 15 V, and the output ripple is only 23 mV. After using 0.18 μm CMOS(Complementary Metal Oxide Semiconductor) technology, the test results meet the programming requirements of Flash FPGA.

Key words: Flash-based FPGA, pogramming, high pressure, cross coupling, parallel double branch, six phase non overlapping clock, ripple, charge pump

中图分类号: 

  • TN433