R-DSP中BSU运算部件的UVM验证

doi:10.16180/j.cnki.issn1007-7820.2025.05.003

电子科技 ›› 2025, Vol. 38 ›› Issue (5): 15-21.doi: 10.16180/j.cnki.issn1007-7820.2025.05.003

R-DSP中BSU运算部件的UVM验证

郭双喜(), 谭勋琼, 白创

长沙理工大学物理与电子科学学院,湖南长沙 410114

收稿日期:2023-10-29 修回日期:2023-11-24 出版日期:2025-05-15 发布日期:2025-05-14
通讯作者: 郭双喜 E-mail:1127962990@qq.com
作者简介:谭勋琼(1967-),男,博士,副教授。研究方向:集成电路设计与验证。
白创(1983-),男,博士,讲师。研究方向:集成电路设计与验证。
基金资助:
湖南省教育厅优秀青年科研项目(22B0287)

UVM Verification of BSU Arithmetic Unit in R-DSP

GUO Shuangxi(), TAN Xunqiong, BAI Chuang

School of Physics and Electronic Science,Changsha University of Science and Technology,Changsha 410114,China

Received:2023-10-29 Revised:2023-11-24 Online:2025-05-15 Published:2025-05-14
Contact: GUO Shuangxi E-mail:1127962990@qq.com
Supported by:
Research Foundation of Education Bureau of Hunan(22B0287)

摘要/Abstract

摘要：

R-DSP(Radar Digital Signal Processor )芯片中BSU(Branch Shift Unit)运算部件具有较大的设计规模和复杂度,传统Verilog验证平台难以满足其验证需求问题。针对该问题,文中采用UVM(Universal Verification Methodology)方法对BSU运算部件进行功能验证。搭建基于SystemVerilog语言实现的UVM验证平台,使用定向测试和带约束的随机测试进行验证,并采用覆盖率驱动的方法指导测试用例的生成,以充分覆盖BSU运算部件的各个功能和代码路径。经过多轮测试激励验证,代码覆盖率接近100%,完成了对BSU运算部件的功能验证。所提方法为R-DSP芯片中的ALU(Arithmetic Logic Unit)、AGU(Address Generation Unit)、MU(Multiplication Unit)等运算部件的验证工作提供了参考和借鉴。

关键词: BSU运算部件, 功能验证, UVM方法, SystemVerilog语言, 定向测试, 约束随机测试, 覆盖率驱动, 代码覆盖率

Abstract:

In view of the problem that the BSU(Branch Shift Unit) arithmetic unit in the R-DSP(Radar Digital Signal Processor) chip has a large design scale and complexity, and the traditional Verilog verification platform is difficult to meet its verification requirements, this study adopts the UVM(Universal Verification Methodology) to conduct functional verification of the BSU arithmetic unit.A UVM verification platform implemented based on the SystemVerilog language is constructed. Directed testing and constrained random testing are utilized for verification, and the coverage-driven approach is adopted to guide the generation of test cases, so as to fully cover all functions and code paths of the BSU arithmetic unit.After multiple rounds of verification with test stimuli, the code coverage approaches 100%, and the functional verification of the BSU arithmetic unit is completed. The proposed method provides a reference for the verification work of arithmetic units such as the ALU(Arithmetic Logic Unit),AGU(Address Generation Unit), and MU(Multiplication Unit) in the R-DSP chip.

Key words: BSU computing unit, functional verification, UVM method, SystemVerilog language, directed test, constrainted random test, coverage driven, code coverage

中图分类号:

郭双喜, 谭勋琼, 白创. R-DSP中BSU运算部件的UVM验证[J]. 电子科技, 2025, 38(5): 15-21.

GUO Shuangxi, TAN Xunqiong, BAI Chuang. UVM Verification of BSU Arithmetic Unit in R-DSP[J]. Electronic Science and Technology, 2025, 38(5): 15-21.

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R-DSP中BSU运算部件的UVM验证

UVM Verification of BSU Arithmetic Unit in R-DSP

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