基于FPGA-TDC的随机同步误差校正电

doi:10.16180/j.cnki.issn1007-7820.2025.06.002

电子科技 ›› 2025, Vol. 38 ›› Issue (6): 9-15.doi: 10.16180/j.cnki.issn1007-7820.2025.06.002

基于FPGA-TDC的随机同步误差校正电

姚晓晨¹, 徐杨¹, 郑其斌¹(), 卜朝晖¹, 唐高明², 崔海坡¹

1.上海理工大学健康科学与工程学院,上海 200093
2.上海航天测控通信研究所,上海 200092

收稿日期:2023-11-27 修回日期:2023-12-29 出版日期:2025-06-15 发布日期:2025-06-24
通讯作者: 郑其斌(1988-),男, Email:qbzheng@usst.edu.cn,博士,副教授。研究方向:高速电路设计、高精度时间测量、高精度能量测量。
作者简介:姚晓晨(1999-),男,硕士研究生。研究方向:高速电路设计、高精度时间测量。
基金资助:
国家自然科学基金(12105177);上海航天科技创新基金(SAST2022-094)

Random Synchronization Error Correction Circuit Based on FPGA-TDC

YAO Xiaochen¹, XU Yang¹, ZHENG Qibin¹(), BU Zhaohui¹, TANG Gaoming², CUI Haipo¹

1. School of Health Science and Engineering,University of Shanghai for Science and Technology,Shanghai 200093,China
2. Shanghai Spaceflight Measurement-Control and Communication Institute,Shanghai 200092,China

Received:2023-11-27 Revised:2023-12-29 Online:2025-06-15 Published:2025-06-24
Supported by:
National Natural Science Foundation of China(12105177);Shanghai Aerospace Science and Technology Innovation Fund(SAST2022-094)

摘要/Abstract

摘要：

针对多通道雷达接收机中随机同步误差导致采集通道间回波信号数据难以对齐的问题,文中设计了一种全数字随机同步误差校正电路。采用基于FPGA-TDC(Field Programmable Gate Array-Time-to-Digital Converter)的高精度时间测量技术测量外触发到达时刻和系统时钟上升沿之间的相位差,根据编码和标定后的相位差信息确定相位补偿步长。采用FPGA混合模式时钟管理器(Mixed-Mode Clock Manager, MMCM)的动态移相模式对时钟进行精细的相位移动,完成系统时钟与脉冲回波信号之间的高精度同步。测试结果表明,所提电路精度优于70 psrms(root mean square),校正时间小于12 μs,能够快速处理随机同步误差问题。

关键词: 随机同步误差, 多通道采集系统, 误差校正, FPGA, 时间数字转换, 相位补偿, 动态移相, MMCM

Abstract:

In view of the problem that the random synchronization error in multiple-channel radar receivers leads to the difficulty in aligning the echo signal data between the acquisition channels, this study designs an all-digital random synchronization error correction circuit. High-precision time measurement technology based on the FPGA-TDC(Field Programmable Gate Array-Time-to-Digital Converter) is used to measure the phase difference between the arrival moment of the external trigger and the rising edge of the system clock. The phase compensation step size is determined from the phase difference information after encoding and calibration. The dynamic phase shifting mode of the MMCM(Mixed-Mode Clock Manager) in the FPGA is used to finely adjust the clock phase, and complete the high-precision synchronization between the system clock and the pulse echo signal. Test results show that the accuracy of the proposed circuit is better than 70 ps rms (root mean square), and the correction time is less than 12 μs, indicating that the proposed method is able to deal with the random synchronization error problem quickly.

Key words: random synchronization error, multiple-channels data acquisition system, error correction, FPGA, time to digital convert, phase compensation, dynamic phase shift, MMCM

中图分类号:

TN791

姚晓晨, 徐杨, 郑其斌, 卜朝晖, 唐高明, 崔海坡. 基于FPGA-TDC的随机同步误差校正电[J]. 电子科技, 2025, 38(6): 9-15.

YAO Xiaochen, XU Yang, ZHENG Qibin, BU Zhaohui, TANG Gaoming, CUI Haipo. Random Synchronization Error Correction Circuit Based on FPGA-TDC[J]. Electronic Science and Technology, 2025, 38(6): 9-15.

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参数	数值
延迟单元N	169
平均延迟T_cell	23.8ps
总延迟时间T	4 022.0ps
TDC时钟Clk_tdc	250MHz
相位补偿工作时钟ps_clk	125MHz
压控振荡器频率F_vco	1 250MHz/1 000MHz
相位补偿步长T_step	14.2ps/17.8ps
最大相位补偿步数S_tM	283/142
单步移相时间	50.0ns

基于FPGA-TDC的随机同步误差校正电

Random Synchronization Error Correction Circuit Based on FPGA-TDC

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