基于RISC-V的高效访存指令扩展与硬件实现

doi:10.16180/j.cnki.issn1007-7820.2025.06.007

电子科技 ›› 2025, Vol. 38 ›› Issue (6): 45-51.doi: 10.16180/j.cnki.issn1007-7820.2025.06.007

基于RISC-V的高效访存指令扩展与硬件实现

徐俊杰¹^,², 张加宏¹, 魏敬和²(), 刘国柱², 何健², 尤兴宇¹^,²

1.南京信息工程大学电子与信息工程学院,江苏南京 210044
2.中国电子科技集团公司第五十八研究所,江苏无锡 214123

收稿日期:2023-10-31 修回日期:2023-12-01 出版日期:2025-06-15 发布日期:2025-06-24
通讯作者: 魏敬和(1970-),男, E-mail:pume1975_cnjs@sina.com,博士,研究员。研究方向:系统芯片设计。
作者简介:徐俊杰(1999-),男,硕士研究生。研究方向:基于RISC-V的MCU设计与应用。
基金资助:
国家自然科学基金(62204233);江苏省自然科学基金(BK20211041);江苏省产业前瞻与关键核心技术重点项目(BE2021003-1);江苏省重点研发计划产业前瞻与关键核心技术项目(BE2023005-1)

Efficient Memory Access Instruction Extension and Hardware Implementation Based on RISC-V

XU Junjie¹^,², ZHANG Jiahong¹, WEI Jinghe²(), LIU Guozhu², HE Jian², YOU Xingyu¹^,²

1. School of Electronics and Information Engineering,Nanjing University of Information Scienof and Technology,Nanjing 210044, China
2. The 58th Research Institute of China Electronics Technology Group Corporation, Wuxi 214123,China

Received:2023-10-31 Revised:2023-12-01 Online:2025-06-15 Published:2025-06-24
Supported by:
National Natural Science Foundation of China(62204233);Natural Science Foundation of Jangsu(BK20211041);Industry Outlook and Key Core Technology Key Projects in Jiangsu(BE2021003-1);Key R&D Plan Industry Outlook and Key Core Technology Projects in Jiangsu(BE2023005-1)

摘要/Abstract

摘要： MCU(Micro Control Unit)是神经网络模型硬件端在部署推理时常用的数据流控制手段,访存操作是MCU数据流控制中的主要执行内容。针对传统指令集架构的MCU所支持的访存指令存在效率低、灵活性差等问题,文中基于RISC-V(Reduced Instruction Set Computer V)指令集展开了SIMD(Single Instruction Multiple Data)扩展研究。根据RISC-V官方预留的指令扩展编码空间设计了高效的访存指令。为支持新扩展指令的正确执行,基于芯来科技开源的蜂鸟E203内核扩展相关硬件电路。通过对比基本内核和扩展内核针对相同功能软件负载的执行结果来评估扩展内核的性能。结果表明扩展E203内核在16 Byte地址空间连续访存时,指令数同比缩减了65.23%,执行周期缩减了66.12%,并且随着访存数量的增加,扩展内核的能效比也越高。

关键词: 指令集扩展, RISC-V指令集架构, SIMD, 蜂鸟E203, 高效访存, 硬件部署, 数据流, 指令缩减

Abstract:

MCU(Micro Control Unit) is a data flow control method often used in the deployment inference of neural network model hardware, and memory access operation is the main execution content of MCU data flow control. In view of the problems such as low efficiency and poor flexibility of memory access instruction supported by MCU with traditional instruction set architecture, this study investigates SIMD(Single Instruction Multiple Data) extension based on RISC-V(Reduced Instruction Set Computer V) instruction set. The efficient memory access instruction is designed according to the instruction expansion coding space reserved by RISC-V. To support the correct execution of the new extension instructions, the related hardware circuit is extended based on the open source Hummingbird E203 kernel of core technology. The performance of the extended kernel is evaluated by comparing the performance of the base kernel and the extended kernel against the same functional software load. The results show that when the extended E203 kernel continuously accesses memory in the 16 Byte address space, the number of instructions is reduced by 65.23%, the execution cycle is reduced by 66.12%, and the energy efficiency of the extended kernel is higher with the increase of the number of accesses.

Key words: instruction extension, RISC-V, SIMD, Hummingbird E203, efficient storage access, hardware deployment, data stream, instruction reduction

中图分类号:

TN431.2

徐俊杰, 张加宏, 魏敬和, 刘国柱, 何健, 尤兴宇. 基于RISC-V的高效访存指令扩展与硬件实现[J]. 电子科技, 2025, 38(6): 45-51.

XU Junjie, ZHANG Jiahong, WEI Jinghe, LIU Guozhu, HE Jian, YOU Xingyu. Efficient Memory Access Instruction Extension and Hardware Implementation Based on RISC-V[J]. Electronic Science and Technology, 2025, 38(6): 45-51.

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inst[6:5]
	000	001	010	011	100	101	110	111
00	LOAD	LOAD-FP	custom0	MISC-MEM	OP-IMM	AUIPC	OP-IMM-32	48 bit
01	STORE	STORE-FP	custom1	AMO	OP	LUI	OP-32	64 bit
10	MADD	MSUB	NMSUB	NMADD	OP-FP	reserve	custom2/rv128	48 bit
11	BRANCH	JALR	reserve	JAL	SYSTEM	reserve	custom3/rv128	≥80 bit

基于RISC-V的高效访存指令扩展与硬件实现

Efficient Memory Access Instruction Extension and Hardware Implementation Based on RISC-V

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