基于车载语音芯片开关电容积分电路设计

doi:10.16180/j.cnki.issn1007-7820.2025.07.007

摘要/Abstract

摘要：

针对Sigma-Delta ADC(Sigma-Delta Analog-to-Digital Converter)高功耗的问题,文中提出一种适用于低功耗高精度语音识别芯片的开关电容积分器。在MATLAB系统建模中提出新建模思路,根据MOS(Metal-Oxide-Semiconductor)管的寄生参数重新定义非理想因子系数,使模型更贴近实际电路。Sigma-Delta调制器模型采用过采样率为128倍的3阶单比特前馈调制器。通过对Sigma-Delta调制器模型仿真可以得到各级积分器系数,为后续使用Cadence软件进行MOS晶体管电路设计提供指导。仿真结果表明Sigma-Delta调制器有效位数可达16.95位,信噪比可达103.8 dB。在0.18 μm工艺下,对Sigma-Delta调制器的第1级积分器电路进行设计,并对第1级开关电容积分器中的运算放大器进行仿真验证,结果表明直流增益可以达到104 dB,增益带宽积为72 MHz,相位裕度为85°,直流静态功耗为915 μW。

关键词: MATLAB, Simulink, Sigma-Delta调制器, 开关电容, 折叠共源共栅运放, 增益增强, 低功耗

Abstract:

In order to cope with the problem of high power consumption of Sigma-Delta AD(Sigma-Delta Analog-to-Digital Converter), a switched capacitor integrator suitable for low-power and high-precision speech recognition chip is proposed. A new modeling idea is proposed in the MATLAB system modeling, and the non-ideal factor coefficients are redefined according to the parasitic parameters of the MOS(Metal-Oxide-Semiconductor) tube, so that the model is closer to the actual circuit. The Sigma-Delta modulator model uses a 3-order single-bit feedforward modulator with an oversampling rate of 128 times. By simulating the Sigma Delta modulator model, the integrator coefficients of all levels can be obtained, which provides guidance for the design of MOS transistor circuit with Cadence software. In the MATLAB system modeling simulation, the simulation results show that the effective bit number of Sigma-Delta modulator can reach 16.95 bits, and the signal-to-noise ratio can reach 103.8 dB. In the process of 0.18 μm, the first-stage integrator circuit of the Sigma-Delta modulator is designed, and the operational amplifier in the first-stage switched-capacitor integrator is simulated and verified. Simulation results show that the DC gain can reach 104 dB, the gain bandwidth product is 72 MHz, the phase margin is 85°, and the DC quiescent power consumption is 915 μW.

Key words: MATLAB, Simulink, Sigma-delta modulator, switched-capacitor, folded cascode, gain boost, low power consumption

中图分类号:

TN713

余鑫, 张轩雄, 李文宏. 基于车载语音芯片开关电容积分电路设计[J]. 电子科技, 2025, 38(7): 50-57.

YU Xin, ZHANG Xuanxiong, LI Wenhong. Design of Switched-Capacitor Circuits Based on on-Board Voice Chip[J]. Electronic Science and Technology, 2025, 38(7): 50-57.

图/表 19

图1

表1

表2

图2

图3

图4

图5

图6

图7

图8

图9

图10

图11

图12

图13

图14

图15

图16

表3

参考文献 24

[1]	Razavi B. Principles of data conversion system design[M]. New York: IEEE Press, 1995:1-5.
[2]	Steiner M, Greer N. 15.8 A 22.3b 1 kHz 12.7 mW switched-capacitor ΔΣ modulator with stacked split-steering amplifiers[C]. San Francisco: IEEE International Solid-State Circuits Conference, 2016:284-286.
[3]	Dolecek G J, Mitra S K. Stepped triangular CIC filter for rational sample rate conversion[C]. Singapore: IEEE Asia Pacific Conference on Circuits and Systems, 2006:916-919.
[4]	王宁, 辛晓宁, 任建, 等. 一种高精度高信噪比的Sigma-Delta调制器设计[J]. 微处理机, 2023, 44(3):23-26.
	Wang Ning, Xin Xiaoning, Ren Jian, et al. Design of a Sigma-Delta modulator with high precision and high signal-to-noise ratio[J]. Microprocessors, 2023, 44(3):23-26.
[5]	魏榕山, 陈林城. 高精度低功耗Sigma-Delta调制器的设计[J]. 电子科技, 2015, 28(10):126-129.
	Wei Rongshan, Chen Lincheng. Design of a high resolution low power Sigma-Delta modulator[J]. Electronic Science and Technology, 2015, 28(10):126-129.
[6]	Markus J, Silva J, Temes G C. Theory and applications of incremental sigma-delta converters[J]. IEEE Transactions on Circuits and Systems I-Regular Papers, 2004, 51(4):678-690.
[7]	Pan H, Abidi A A. Spectral spurs due to quantization in Nyquist ADCs[J]. IEEE Transactions on Circuits and Systems I:Regulator Papers, 2004, 51(8):1422-1439.
[8]	Richard S, Gabor C T. Understanding delta-sigma data converters[M]. Hoboken: Wiley IEEE Press, 2005:168-180.
[9]	孔梦华, 卜刚, 吴振淇. 低功耗Sigma-Delta调制器的建模与设计[J]. 电子科技, 2016, 29(9):136-138.
	Kong Menghua, Bu Gang, Wu Zhenqi, Modeling and design of the low-power Sigma-Delta modulator[J]. Electronic Science and Technology, 2016, 29(9):136-138.
[10]	刘振宇, 宋树祥, 岑明灿, 等. 低功耗高精度Sigma-Delta调制器的建模与设计[J]. 广西师范大学学报(自然科学版), 2022, 40(2):58-70.
	Liu Zhenyu, Song Shuxiang, Cen Mingcan. Modeling and design of low power and high precision sigma-delta modulator[J]. Journal of Guangxi Normal University(Natural Science Edition), 2022, 40(2):58-70.
[11]	Yang Y Q, Chokhawala A, Alexander M, et al. A 114 dB 68 mW chopper-stabilized stereo multibit audio ADC in 5.62 mm²[J]. IEEE Journal of Solid-State Circuits, 2003, 38(12):2061-2068.
[12]	Roh J, Byun S, Choi Y, et al. A 0.9 V 60 μW 1 Bit fourth-order delta-sigma modulator with 83-dB dynamic range[J]. IEEE Journal of Solid-State Circuits, 2008, 43(2):361-370.
[13]	Wang B, Sin S W, Seng U, et al. A 550μW 20 KHz BW 100.8 dB SNDR linear-exponential multi-bit incremental sigma-delta ADC with 256 clock cycles in 65 nm CMOS[J]. IEEE Journal of Solid-State Circuits, 2019, 54(4):1161-1172.
[14]	Quiquempoix V, Deval P, Barreto A, et al. A low-power 22 bit incremental ADC[J]. IEEE Journal of Solid-State Circuits, 2006, 41(7):1562-1571.
[15]	Geerts Y, Steyaert M S J, Sansen W. A high-performance multibit ΔΣ CMOS ADC[J]. IEEE Journal of Solid-StateCircuits, 2000, 35(12):1829-1840.
[16]	Park H, Nam K, Su D K, et al. A 0.7 V 870 μW digital-audio CMOS sigma-delta modulator[J]. IEEE Journal of Solid-State Circuits, 2009, 44(4):1078-1088.
[17]	Tang Y, Cheng K W, Gupta S, et al. Cascaded complex ADCs with adaptive digital calibration for I/Q mismatch[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2008, 55(3):817-827.
[18]	Kwon C K, Kim H, Park J, et al. A 0.4 mW,4.7 ps resolution single-loop ΔΣ TDC using a half-delay time integrator[J]. IEEE Transactions on Very Large Scale Integration Systems, 2015, 24(3):1184-1188.
[19]	Li D, Qian X, Li R, et al. High resolution ADC for ultrasound color doppler imaging based on MASH sigma-delta modulator[J]. IEEE Transactions on Biomedical Engineering 2019, 67(5):1438-1449.
[20]	Sackinger E, Guggenbuhl W. A high-swing, high impedance MOS cascade circuit[J]. IEEE Journal of Solid-State Circuits, 1990, 25(1):289-298.
[21]	郑凯伦, 郭桂良. 一种高增益高电流效率的运算跨放大器[J]. 微电子学与计算机, 2020, 37(6):51-56.
	Zheng Kailun, Guo Guiliang. A high-gian high-current-efficiency OTA[J]. Microelectronics & Computer, 2020, 37(6):51-56.
[22]	Sarkar S, Ghosh A, Chatterjee T. Design of a 2 mW power, 112 dB gain-boosted,folded cascode amplifier in 0.18 μm process[C]. Kyoto: IEEE the Thirtieth International Symposium on Industrial Electronics, 2021:1-5.
[23]	Navidi R, Fathi A, Mohammadi K, et al. Improved gain folded cascode opamp employing a novel positive feedback structure[C]. Yazd: The Twenty-seventh Iranian Conference on Electrical Engineering, 2019:269-273.
[24]	彭春雨, 张伟强, 蔺智挺, 等. 一种高增益、高带宽全差分运算放大器的设计[J]. 电子与封装, 2023, 23(7):57-62.
	Peng Chunyu, Zhang Weiqiang, Lin Zhiting, et al. Design of a high gain,high bandwidth,fully differential operational amplifier[J]. Electronics & Packaging, 2023, 23(7):57-62.

前馈系数	输入信号前馈系数	积分器增益系数	反馈增益系数
a₁=2	b₁=0.2	c₁=0.2	g₁=0
a₂=2	b₂=0.0	c₂=0.3
a₃=2	b₃=0.0	c₃=0.3
	b₄=1.0

前馈系数	输入信号前馈系数	积分器增益系数	反馈增益系数
a₁=2.4	b₁=0.22	c₁=0.2	g₁=0
a₂=3.3	b₂=0.00	c₂=0.3
a₃=3.0	b₃=0.00	c₃=0.2
	b₄=0.85

文献	工艺参数/ nm	电源电压/ V	直流增益/ dB	相位裕度/ (°)	功耗/ mW	压摆率/ V·μs^-1
文献[22]	180	2.0	12.0	67	2.00	44
文献[23]	180	1.8	75.6	84	8.44	-
文献[24]	55	1.8	115.0	71	2.80	-
本文	180	1.8	108.0	85	0.90	20