[1]YONG J H,JAE H L,TAE H H.3D network-on-chip system communication using minimum number of TSVs[C].ICTC,2011:517-522.
[2]RAHMANI A M,LATIF K,LILJEBERG P,et al.Research and practices on 3D networks-on-chip architectures[C].Proceeding of Norchip,2010.
[3]MARINISSEN E J,ZORIAN Y.Testing 3D chips containing through-silicon vias[C].International Test Conference,2009:1-11.
[4]COTA E,LIU C.Constraint-driven test scheduling for NoC-based systems[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2006,25(11):2465-2478.
[5]欧阳一鸣,冯伟,梁华国.功耗限制下的NoC测试端口的优化选择方法[J].计算机应用,2008,28(4):204-206,209.
[6]CHAN M J,HSU C L.A strategy for interconnect testing in stacked mesh network on chip[C].Proceeding of IEEE International Symposium on Defect and Tolerance in VLSI Systems,2010:122-128.
[7]欧阳一鸣,刘蓓,齐芸.三维片上网络测试的时间优化方法[C].合肥:第六届中国测试学术会议,2010:332-336.
[8]张光卫,何锐,刘禹,等.基于云模型的进化算法[J].计算机学报,2008,31(7):1082-1091.
[9]侯绪彬.基于云进化算法的NoC测试规划[J].电子科技,2013,26(9):1-3.
[10]许川佩,姚芬,胡聪.基于云进化算法的NoC资源节点优化测试研究[J].电子测量与仪器学报,2012,26(3):192-196. |