›› 2015, Vol. 28 ›› Issue (3): 99-.

• 论文 • 上一篇    下一篇

一种基于AHB总线的存储控制器设计

刘少龙   

  1. (海装重庆局,四川 成都 610100)
  • 出版日期:2015-03-15 发布日期:2015-03-12
  • 作者简介:刘少龙(1976—),男,工程师。研究方向:航空电子设计。E-mail:nizhenming12121@163.com

Design of a Memory Controller Based on AHB Bus

LIU Shaolong   

  1. (Navy Armament Department,Chengdu 610100,China)
  • Online:2015-03-15 Published:2015-03-12

摘要:

介绍一种能兼容高速总线AHB的存储控制器结构,其充分利用AMBA2.0协议对高速总线通信方式的规定,实现了对外部RAM和ROM的高效访问控制。该控制器结构在完成总线端和存储端时序转换的基础上,对系统访问中的获取指令、写操作及原子操作进行了优化设计,提高了此类操作的访问效率。此外,本设计采用异步时钟域的设计方法,降低了控制器在空闲状态下的动态功耗。该IP采用硬件描述语言设计,核心部件采用有限状态机实现,最终形成可复用的IP软核。

关键词: AHB, 存储控制器, 原子操作, 低功耗

Abstract:

The paper presents a memory controller IP core based on high-speed bus.It takes full advantage of the protocol of AMBA 2.0 to achieve efficient access to the external RAM and ROM.With the implement of timing transition between bus-end and memory-end,the memory controller realizes the timing optimization for three special operations:instruction fetch,write access and atomic operation,improving the access efficiency for those behaviors.Additionally,this design adopts an asynchronous design method for the whole circuit,which reduces the power of controller under the idle state.This IP is described by VHDL,whose hardcore is implemented with FSM (Finite State Machine),thus forming a reusable soft core.

Key words: AHB;memory controller;atomic operation;low power

中图分类号: 

  • TN492