关键词: 现场可编程门阵列, 快速傅立叶变换, 基4蝶形运算, 硬件描述语言

Abstract:

A 1024-point FPGA-based 16-bit FFT algorithm is designed which is using the Radix-4 butterfly algorithm and pipeline operations to enhance the processing speed and improve the performance.A structure that the butterfly operation of the first level is made before the complex multiplication of the rotation factor of the second level is proposed,which is using of the hardware resources reasonably.The system is divided into several modules in Verilog HDL.After testing the function of system,the results ofjoint simulation of QuartusⅡ and Matlab is consistent.The system not only achieves the flexibility of DSP devices but also has the high-speed data throughput of dedicated FFT chips.This algorithm can be
widely used in the field of digital signal processing.

Key words: FPGA;FFT;radix-4 butterfly algorithm;Verilog HDL