基于优化BPNN的FPGA内嵌高速接口总抖动预测方法

doi:10.16180/j.cnki.issn1007-7820.2025.02.009

Abstract

Abstract:

In view of the problem that ATE(Automated Test Equipment) can not measure the total jitter of FPGA(Field-Programmable Gate Array) embedded high-speed interface directly, this study presents a method to predict the total jitter of high-speed interface based on optimized BPNN(Back Propagation Neural Network). The GA-BP neural network is formed to optimize the initial weight and parameter seeking process of BPNN using the strong global search ability of GA(Genetic Algorithm), and improve the accuracy of predicting the total jitter. The GA_BP total jitter prediction model was constructed using MATLAB software to predict and optimize the screened jitter data. The experimental results show that compared with the non-optimized BP neural network and the traditional Elman neural network prediction model, the mean square error of the GA_BP prediction model is declined by 75.5% and 88.0%, and the number of iterations is reduced by 68.0% and 59.8%, respectively. It indicates that the proposed GA_BP model has higher prediction accuracy and iteration efficiency, and can be applied to total jitter production test in ATE.

Key words: high-speed interface, total jitter prediction, optimized BP neural network, genetic algorithm, Grubbs criterion, FPGA, mean square error, production test

CLC Number:

TP27

YE Xiangyu, LIN Xiaohui, DING Jiangqiao, XIE Weikun. Total Jitter Prediction Method of FPGA Embedded High-Speed Interface Based on Optimized BPNN[J].Electronic Science and Technology, 2025, 38(2): 70-77.

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References 18

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节点数S	MSE	迭代次数
4	0.183 569	29
5	0.178 967	35
6	0.165 894	39
7	0.156 375	42
8	0.134 827	44
9	0.119 563	39
10	0.107 652	33
11	0.106 876	46
12	0.106 751	50
13	0.106 388	52

模型	相关系数R²	MSE	MAE	RMSE	迭代次数
GA_BP	0.969 3	0.107 3	0.273 6	0.327 5	41
未优化的BP	0.874 9	0.437 3	0.619 3	0.661 2	128
传统Elman	0.744 2	0.893 9	0.907 2	0.945 4	102

Total Jitter Prediction Method of FPGA Embedded High-Speed Interface Based on Optimized BPNN

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