隔离驱动芯片高速编解码电路设计

doi:10.16180/j.cnki.issn1007-7820.2025.02.011

Abstract

Abstract:

A digital isolator encoding and decoding scheme for isolation drive circuits is designed using the isolation transmission method of stacked micro on-chip transformers. In view of the high radio frequency modulation power consumption, pulse modulation rate limitations, and reliability issues in existing isolator mainstream encoding and decoding schemes, single and double pulse encoding and decoding technology is adopted to reduce power consumption and optimize encoding and decoding methods in this study. Compared with traditional single and double pulse decoding methods, replacing the sampled pulse signal in the decoding circuit with an edge triggered signal improves reliability, increases signal transmission rate by nearly twice, reduces delay time, and combines refresh timing circuit and watchdog circuit to achieve reliable transmission of digital isolators. The experimental results show that the digital signal achieves isolated transmission of DC~90 Mbit·s^-1. The overall static power consumption of encoding and decoding is 0.574 mA, the dynamic power consumption is 0.257 mA·(Mbit·s^-1)^-1, the delay time is less than 18 ns, and the pulse width distortion is less than 2 ns.

Key words: on chip transformer, digital isolator, encoding and decoding, pulse modulation, high speed, low latency, high reliability, low power consumption

CLC Number:

TN432

XIONG Zhangliang, CHEN Suting, XUAN Zhibin, ZHAO Tingchen, LIU Jiajun, FU Mannan. Design of High Speed Encoding and Decoding Circuit for Isolation Driver Chip[J].Electronic Science and Technology, 2025, 38(2): 84-92.

Figures/Tables 15

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References 17

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编码侧	功耗/μA	解码侧	功耗/μA
偏置电路	124.3	偏置电路	125.9
欠压锁定	31.2	欠压锁定	43.1
上电复位	43.6	上电复位	38.5
1 μs计时电路	62.4	5 μs计时电路	11.3
其他	58.5	其他	35.7
总计	320.0	总计	254.5

参数	最小值	典型值	最大值	传输速率/Mbit·s^-1
IDD₁	0.16	0.21	0.28	1
IDD₂	0.05	0.08	0.12	1
IDD₁	1.98	2.12	2.36	10
IDD₂	0.43	0.51	0.61	10
IDD₁	10.87	11.36	12.07	50
IDD₂	2.09	2.28	2.31	50
IDD₁	19.52	19.87	20.55	90
IDD₂	3.86	4.13	4.43	90

参数	文献[7]	文献[14]	本文
工艺/μm	0.500	0.18	0.250
传播延时/ns	20.000	50.00	18.000
最大速率/Mbit·s^-1	40.000	30.00	90.000
脉宽失真/ns	<3	<3	<2
静态功耗/mA	0.570	2.50	0.574
动态功耗/mA·(Mbit·s^-1)^-1	0.213	0.70	0.257

Design of High Speed Encoding and Decoding Circuit for Isolation Driver Chip

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