应用于Flash型FPGA的正高压电荷泵

doi:10.16180/j.cnki.issn1007-7820.2025.03.010

Abstract

Abstract:

When Flash-based FPGA(Filed Programmable Gate Array) performs programming operations, the charge pump provides positive high voltage to the gate end of the programming tube. In order to meet the power on timely operation, and programming stability of Flash-based FPGA, the charge pump is required not only be able to output high voltage, but also have fast startup speed and small output voltage ripple. This study proposes a positive high-voltage charge pump based on the traditional cross coupled charge pump. The main body of the charge pump adopts a parallel dual branch structure, reducing the output voltage ripple. It uses a six phase non overlapping clock and a new clock boost module to control the timing of the charge pump, eliminating the impact of reverse current and improving the start speed of the charge pump. A voltage stabilizing module is set at the output end for voltage regulation, ensuring programming stability. The simulation results show that under the conditions of 3.3 V supply voltage, 20 MHz clock frequency and 50 pF load capacitance, the charge pump startup time is 6.6 μs, the output voltage is stable to 15 V, and the output ripple is only 23 mV. After using 0.18 μm CMOS(Complementary Metal Oxide Semiconductor) technology, the test results meet the programming requirements of Flash FPGA.

Key words: Flash-based FPGA, pogramming, high pressure, cross coupling, parallel double branch, six phase non overlapping clock, ripple, charge pump

CLC Number:

TN433

JIANG Shaoxiang, YU Shenglin, MA Jinlong, WU Chubin. Positive High Voltage Charge Pump Applied to Flash-Based FPGA[J].Electronic Science and Technology, 2025, 38(3): 75-81.

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Table 1.

References 18

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参数	文献[7]	文献[8]	本文
工艺/μm	0.34	0.18	0.18
级数	4	9	9
上升时间/μs	5.00	6.80	6.60
输出电压/V	9.00	15.00	15.00
纹波/mV	70.00	38.50	23.00

Positive High Voltage Charge Pump Applied to Flash-Based FPGA

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