Electronic Science and Technology ›› 2025, Vol. 38 ›› Issue (3): 82-87.doi: 10.16180/j.cnki.issn1007-7820.2025.03.011

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Handshake Protocol Design of Transceiver Module Based on FPGA High-Speed Serdes Interface

LIU Zhengqiang1(), HONG Xujian1, SUN Weihong2   

  1. 1. Electronic and Electrical Research Institute,Shanghai Sansi Electronic Engineering Co., Ltd.,Shanghai 201100,China
    2. College of Mechanical and Electrical Engineering,China Jiliang University,Hangzhou 310018,China
  • Received:2023-09-19 Revised:2023-10-17 Online:2025-03-15 Published:2025-03-11
  • Supported by:
    National Key R&D Program of China(2017YFB0403500)

Abstract:

In order to improve the stability of FPGA(Field Programmable Gate Array) high-speed Serdes communication and monitor its communication status in real time, a communication protocol based on K-code control characters is designed. Two K-code control characters, dynamic SOF(Start of Frame) that marks the start of user data frames and static EOF(End of Frame) that marks the end, are created to facilitate the continuity detection of communication. K-code control characters TLINK(Transmit Link) and BLINK(Back Link) are created, where the TLINK control character is sent regularly at the Serdes sender. After the Serdes receives the TLINK control character, it controls the sender of its own side to output the BLINK control character for feedback, establishing a handshake relationship between the two communicating parties, which is beneficial for communication timeout and status detection. Verifying user data independent of SOF and EOF for CRC32(Cyclic Redundancy Check32) calculation is beneficial for communication error detection. The experimental results show that the protocol can accurately monitor the number of frame losses, error codes, timeouts, and communication disconnection duration of the Serdes link, with a minimum time accuracy of 10 μs.

Key words: FPGA, Serdes, transceiver module, K-code, handshake protocol, communication monitoring, SOF, EOF

CLC Number: 

  • TN913