基于FPGA-TDC的随机同步误差校正电

doi:10.16180/j.cnki.issn1007-7820.2025.06.002

Abstract

Abstract:

In view of the problem that the random synchronization error in multiple-channel radar receivers leads to the difficulty in aligning the echo signal data between the acquisition channels, this study designs an all-digital random synchronization error correction circuit. High-precision time measurement technology based on the FPGA-TDC(Field Programmable Gate Array-Time-to-Digital Converter) is used to measure the phase difference between the arrival moment of the external trigger and the rising edge of the system clock. The phase compensation step size is determined from the phase difference information after encoding and calibration. The dynamic phase shifting mode of the MMCM(Mixed-Mode Clock Manager) in the FPGA is used to finely adjust the clock phase, and complete the high-precision synchronization between the system clock and the pulse echo signal. Test results show that the accuracy of the proposed circuit is better than 70 ps rms (root mean square), and the correction time is less than 12 μs, indicating that the proposed method is able to deal with the random synchronization error problem quickly.

Key words: random synchronization error, multiple-channels data acquisition system, error correction, FPGA, time to digital convert, phase compensation, dynamic phase shift, MMCM

CLC Number:

TN791

YAO Xiaochen, XU Yang, ZHENG Qibin, BU Zhaohui, TANG Gaoming, CUI Haipo. Random Synchronization Error Correction Circuit Based on FPGA-TDC[J].Electronic Science and Technology, 2025, 38(6): 9-15.

Figures/Tables 12

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References 25

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参数	数值
延迟单元N	169
平均延迟T_cell	23.8ps
总延迟时间T	4 022.0ps
TDC时钟Clk_tdc	250MHz
相位补偿工作时钟ps_clk	125MHz
压控振荡器频率F_vco	1 250MHz/1 000MHz
相位补偿步长T_step	14.2ps/17.8ps
最大相位补偿步数S_tM	283/142
单步移相时间	50.0ns

Random Synchronization Error Correction Circuit Based on FPGA-TDC

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