基于RISC-V的高效访存指令扩展与硬件实现

doi:10.16180/j.cnki.issn1007-7820.2025.06.007

Abstract

Abstract:

MCU(Micro Control Unit) is a data flow control method often used in the deployment inference of neural network model hardware, and memory access operation is the main execution content of MCU data flow control. In view of the problems such as low efficiency and poor flexibility of memory access instruction supported by MCU with traditional instruction set architecture, this study investigates SIMD(Single Instruction Multiple Data) extension based on RISC-V(Reduced Instruction Set Computer V) instruction set. The efficient memory access instruction is designed according to the instruction expansion coding space reserved by RISC-V. To support the correct execution of the new extension instructions, the related hardware circuit is extended based on the open source Hummingbird E203 kernel of core technology. The performance of the extended kernel is evaluated by comparing the performance of the base kernel and the extended kernel against the same functional software load. The results show that when the extended E203 kernel continuously accesses memory in the 16 Byte address space, the number of instructions is reduced by 65.23%, the execution cycle is reduced by 66.12%, and the energy efficiency of the extended kernel is higher with the increase of the number of accesses.

Key words: instruction extension, RISC-V, SIMD, Hummingbird E203, efficient storage access, hardware deployment, data stream, instruction reduction

CLC Number:

TN431.2

XU Junjie, ZHANG Jiahong, WEI Jinghe, LIU Guozhu, HE Jian, YOU Xingyu. Efficient Memory Access Instruction Extension and Hardware Implementation Based on RISC-V[J].Electronic Science and Technology, 2025, 38(6): 45-51.

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inst[6:5]
	000	001	010	011	100	101	110	111
00	LOAD	LOAD-FP	custom0	MISC-MEM	OP-IMM	AUIPC	OP-IMM-32	48 bit
01	STORE	STORE-FP	custom1	AMO	OP	LUI	OP-32	64 bit
10	MADD	MSUB	NMSUB	NMADD	OP-FP	reserve	custom2/rv128	48 bit
11	BRANCH	JALR	reserve	JAL	SYSTEM	reserve	custom3/rv128	≥80 bit

Efficient Memory Access Instruction Extension and Hardware Implementation Based on RISC-V

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