Abstract:

Timing verification is an important step in the process of chip verification, and timing model is the basis of timing verification. Different time series modeling methods should be adopted for PTL(Pass-Transistor Logic) full adder units of different structural types, and the modeling methods should be evaluated from the aspects of applicability, accuracy and timeliness. For the conventional structural standard unit, its circuit structure is more regular and there are more units of this type, so it is more efficient to use the mainstream time sequence database extraction tool for time sequence modeling. For special structural units, the circuit structure is complex and changeable, and the mainstream time sequence library extraction tool cannot be applied, but the number of such units in the module is small, and the complete time sequence modeling can be successfully achieved using the circuit simulation manual time sequence modeling method. After the time series modeling is completed, the time series analysis and power consumption analysis of the multiplier composed of different types of full adder units are carried out. The results show that the rise and fall delay of the multiplier based on PTL full adder unit are reduced by 16.2% and 18.1% respectively, and the power consumption is reduced by 10.8%. In the subsequent engineering application, the time series modeling method can be reasonably adjusted according to different unit types, which has important practical application value.

Key words: PTL, full adder, standard cell, cell timing library, timing modeling, timing analysis, power consumption analysis, engineering application