基于FPGA的线性卷积的实时实现

Abstract

Abstract:

An implementation of fast computing linear convolution based on Fast Fourier Transform is proposed.With the hardware plant based on the Altera's EP2S60,the throughput of the whole system with Altera's FFT IP core is as high as 100 Msps under the 100 MHz system clock.

Key words: FFT;convolution;FPGA

CLC Number:

TN911.72

Cite this article

FAN Hai-Bo. Real-time Implementation of Linear Convolution Based on FPGA[J]., 2010, 23(5): 58-.

share this article

0
/ / Recommend

Add to citation manager EndNote|Reference Manager|ProCite|BibTeX|RefWorks

URL: https://journal.xidian.edu.cn/dzkj/EN/

https://journal.xidian.edu.cn/dzkj/EN/Y2010/V23/I5/58

References

［1］胡广书.数字信号处理-理论、算法与实现［M］.北京:清华大学出版社,1997.

［2］奥本海默.离散时间信号处理［M］.刘树棠,黄建国,译.西安:西安交通大学出版社,2001.

［3］Altera Conpration.FFT MegaCore Function User Guide［Z/OL］.(2004-07-12)［2010-02-12］
www.altera.com.

［4］Altera Conpration.Altera Stratix II Device Handbook［Z/OL］.(2005-12-10)［2010-02-01］
www.altera.com.

［5］Linear Conpration.Linear LTC2280 Datasheet［Z/OL］.(2005-10-03)［2010-01-15］
www.linear.com.

［6］Analog Conpration.Analog AD9763 Datasheet［Z/OL］.(2008-05-11)［2010-01-15］www.analog.com.

Related Articles 15

[1]	LEI Wen，WANG Zhenzhen，MA Huihui，LUO Wei，ZHENG Ning. Design of Pointer type Instrument Recognition System Based on ADSP-BF609 [J]. , 2017, 30(9): 60-.
[2]	LI Yulin，XIANG Yu，WU Song. Noise Source Identification Based on Acoustic Holography and DSP Implementation [J]. , 2017, 30(4): 27-.
[3]	TANG Guangjie, ZHANG Renjie. Research on Capture and Tracking Algorithm of GPS Satellite [J]. , 2016, 29(10): 33-.
[4]	YU Yang,LI Xiaoyan,ZHANG Xiaochun. Automatic Modulation Recognition of BPSK,QPSK,UQPSK,and 64QAM Signals [J]. , 2015, 28(1): 49-.
[5]	CHENG Yao. Frequency Detection with Apfft and Phase Deduction Based on FPGA [J]. , 2015, 28(1): 143-.
[6]	HUI Tengfei,YANG Lei,GONG Xianfeng. An FPGA Implementation Structure of Digital Group Demultiplexing [J]. , 2014, 27(12): 137-.
[7]	Liu Xing. Design of High-speed and High-precision Data Acquisition system Based on ARM and CPLD [J]. , 2014, 27(8): 190-.
[8]	LI Daxi. Research on and Implementation of Reconfigurable FFT IP Core Based on FPGA [J]. , 2014, 27(6): 46-.
[9]	LIU Xiaoguang,DONG Yang,QU Qian,WANG Bing,DENG Jie. Design and Implementation of Blind Recognition of Linear Space-Time Block Codes Based on DSP [J]. , 2014, 27(4): 131-.
[10]	KANG Kang,HE Meng. Design of Bootload for TMS320C6455 DSP Based on the External Flash [J]. , 2014, 27(3): 89-.
[11]	YANG Feifei,YIN Yafang. New Variable Step Size LMS Adaptive Algorithm [J]. , 2013, 26(5): 125-.
[12]	JIA Zhen-Yue, MA Zhi-Gang, YANG Chuan-Chuan. SPI Flash Procedures-load of ADSP-BF53x Series of DSP [J]. , 2013, 26(4): 150-.
[13]	DENG Ke,FAN Junfeng,LIN Ying. Multi-Channel Single-Ended/Differential Signal Sampling and Acquisition System Based on DSP+FPGA [J]. , 2013, 26(3): 33-.
[14]	CHEN Bin,SU Yuxiao. Design of a Fuze Signal Processor with Orient Identification Based on Multi-core Units [J]. , 2013, 26(1): 77-.
[15]	GAO Tonghui,GUO Rui. Design of an ARM-based Intelligence Home Trash Can [J]. , 2012, 25(11): 55-.

Metrics

Viewed

Full text

Abstract

Cited

Shared

Comments

Recommended 0

No Suggested Reading articles found!

Abstract
References
Related Articles
Metrics
Comments
Recommended

TOP

Real-time Implementation of Linear Convolution Based on FPGA

PDF (PC)

Like

Knowledge