Abstract:

Aiming at the problem of high-speed signal integrity and timing mach in the DDRⅡ design,this paper presents the simulation design of PCB which includes DDRⅡ memory through the use of Cadence software.Cadence software is adopted to make topology of DDRⅡ signals and to get the parameters related to signal integrity,such as crosstalk,ISI,overshoot and so on.The parameters related to timing sequence of DDRⅡ signals can be obtained from the simulation waveform,and thereby the timing budget for DDRⅡ signals can be calculated to make constraints for them for the layout.After the layout,the post-route simulation is done in order to identify the signal integrity and timing sequence of the DDRⅡ signals.Some design guidelines are summarized based on the simulation results.

Key words: topology;simulation;signal integrity;signal quality;timing