›› 2011, Vol. 24 ›› Issue (12): 72-.

• Articles • Previous Articles     Next Articles

IP Core Design of SVPWM Based on Nios II Processor

 DU Xiao   

  1. (Institute of Physics and Electronic Technology,Yancheng Teachers College,Yancheng 224002,China)
  • Online:2011-12-15 Published:2011-12-16

Abstract:

In order to reduce the algorithm complexity of FPGA implementation for 3-level SVPWM and the resources occupied by the SVPWM module,the paper proposes a new SVPWM control algorithm by using the small capacity ROM and the relationship between sine and cosine functions.The hardware design of the algorithm is implemented by using Verilog HDL,and packaged into IP cores to facilitate design reuse.The design is tested and verified by Altera's DE2 board,which shows the flexibility and expandability of the SOPC embedded system.

Key words: active inverter;SVPWM;IP Core;SOPC

CLC Number: 

  • TP271+.5