›› 2011, Vol. 24 ›› Issue (12): 88-.

• Articles • Previous Articles     Next Articles

Design and Simulation of the FFT for the FPGA-Based High-precision Floating Point Unit

 ZHANG Xue-Jiao, WU Ping-Hui   

  1. (College of Information Engineering,Hebei University of Technology,Tianjin 300401,China)
  • Online:2011-12-15 Published:2011-12-16

Abstract:

Based on the IEEE floating point format and the FFT algorithm,this paper puts forward a 2FFT-based method based on FPGA.It completes the FFT design for the FPGA-based high-precision floating point unit.It describes the butterfly process and address generation unit processes by using VHDL.The simulation waveform can basically shows the output results correctly.

Key words: FFT;floating point;butterfly process;VHDL

CLC Number: 

  • TN79