›› 2011, Vol. 24 ›› Issue (12): 88-.
• Articles • Previous Articles Next Articles
ZHANG Xue-Jiao, WU Ping-Hui
Online:
Published:
Abstract:
Based on the IEEE floating point format and the FFT algorithm,this paper puts forward a 2FFT-based method based on FPGA.It completes the FFT design for the FPGA-based high-precision floating point unit.It describes the butterfly process and address generation unit processes by using VHDL.The simulation waveform can basically shows the output results correctly.
Key words: FFT;floating point;butterfly process;VHDL
CLC Number:
ZHANG Xue-Jiao, WU Ping-Hui. Design and Simulation of the FFT for the FPGA-Based High-precision Floating Point Unit[J]., 2011, 24(12): 88-.
0 / / Recommend
Add to citation manager EndNote|Reference Manager|ProCite|BibTeX|RefWorks
URL: https://journal.xidian.edu.cn/dzkj/EN/
https://journal.xidian.edu.cn/dzkj/EN/Y2011/V24/I12/88
[1]程佩青.数字信号处理教程[M].2版.北京:清华大学出版社,2001.
[2]马强.基于FPGA的快速傅里叶变换实现[D].南京:南京理工大学,2005.
[3]IEEE Orgnzation.IEEE Standard for Binary Floating-Point Arithmetic,ANSI/IEEE Std 754-1985[S].USA:IEEE Orgnzation,1985.
[4]BAESE M U.数字信号处理的FPGA实现[M].2版.刘凌,译.北京:清华大学出版社,2006.
[5]胡广书.数字信号处理理论、算法与实现[M].北京:清华大学出版社,2003.
Cited