Abstract:

This article introduces the method of using asynchronous FIFO in communication between FPGA and DSP.The FPGA writes the data into FIFO under the control of the writing clock.After hand shaking with the FPGA,the DSP reads the data through the EMIFA interface.The article gives the detailed codes for asynchronous FIFO and the electric circuits for DSP.It is shown that the application of the asynchronous FIFO method in the communication between FPGA and DSP has the advantages of high transmission speed,stability,reliability and easy realization.

Key words: asynchronous FIFO;communication between FPGA and DSP;EMIFA