Abstract:

Aiming at the requirement of reliability,high data management efficiency as well as hardware cost of the airborne information acquisition system,this article mainly introduces the interface conversion of Sdx-bus and Wishbone-bus.The implementation of the design is based on Verilog HDL Language.It is simulated on the ModelSim software,synthesized on the Quartus platform and tested through FPGA from The Cyclone Ⅲ by Altera company.The results show that the design is feasible.

Key words: Verilog HDL;SDX-bus;Wishbone-bus;Modelsim;QuartusⅡ