›› 2012, Vol. 25 ›› Issue (12): 49-.

• Articles • Previous Articles     Next Articles

Design and Implementation of the Mass Data Fast Transmission Module Between Nios II and FPGA Based on DMA

YANG Li-Cheng, LIU Dan-Feng, SHI Ji-Hui   

  1. (1.Satellite Communication Station,Unit 63716 of PLA,Xizhou 036301,China;
    2.Technical Room,Unit 63886 of PLA,Luoyang 471000,China)
  • Online:2012-12-15 Published:2013-02-28

Abstract:

In view of the fact that DMA module can not read/write FPGA peripherals directly in SOPC solutions of Altera company,this paper puts forward the design of general DMA read/write control module based on the transmission mode of Avalon bus flow.The design of two custom peripherals makes it possible for DMA to access High-speed data of FPGA peripherals.It implements rapid transmission of bulk data between the Nios II and FPGA.The paper briefly introduces the Avalon-MM bus norms,and elaborates the design of system architecture and read controller of DMA.Finally the test results show that the solution is efficient and feasible.

Key words: SOPC;Nios II;DMA;avalon bus

CLC Number: 

  • TN06