›› 2012, Vol. 25 ›› Issue (6): 95-.

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A High Speed Low Power LVDS Receiver Design

 SUN Jin-Zhong, XIE Feng-Ying   

  1. (IC Design Center,China Electronic Technology Group Corporation No.38 Research Institute,Hefei 230031,China)
  • Online:2012-06-15 Published:2012-08-23


LVDS system link structure and data transmission principle,LVDS standard receiver circuit,based on 65 nm digital CMOS process design to achieve a high-speed low-power LVDS receiver circuit.The simulation results show that the supply voltage of 2.5 V,the LVDS receiver with 2 Gbit·s-1 data transfer rate,average power consumption is 3 mW.

Key words: low-voltage differential signaling;receiver;differential signal;high speed

CLC Number: 

  • TN432