›› 2013, Vol. 26 ›› Issue (10): 101-.

• Articles • Previous Articles     Next Articles

Sensitivity Analysis of Power Supply Noise of Digital PLL

WANG Yiting   

  1. (Institute of Electronic CAD,Xidian University,Xi'an 710071,China)
  • Online:2013-10-15 Published:2013-10-23


The methodology of the I/O signal jitter affected by power supply noise is presented,which is a breakthrough to the design idea of pure pursuit of low noise for the special power integrity.The concept of jitter sensitivity is verified.The PLL model is used to draw the curve of sensitivity,which suggests that intermodulation exists among different frequency noises.

Key words: sensitivity of noise;intermodulation;phase locked loop;power integrity

CLC Number: 

  • TN401