Abstract:

Based on the principle of DES algorithm and the method of pipeline design and time division multiplexing design,the paper introduces two different ways to implement the algorithm with Xilinx FPGA using respective methods.A detail analysis of the running speed and hardware resource cost between the designs is made.The fastest implementation of the design can achieve a highest clock frequency of 139MHz and an encryption rate of 8.9 Gbit·s^-1.

Key words: DES;pipeline;time division multiplexing;Xilinx FPGA