基于图像处理的版图优化方法

Abstract

Abstract:

In this paper,a method for optimizing layout based on image processing is proposed to improve the yield.The two waited-optimization nets and their movable space are first determined.Then the optimal location of removing waited-optimization net in movable space is separately found out.The waited-optimization net is used as the removing net to optimize layout this time that the maximum critical area is reduced through removing the waited-optimization net.Not only is the true contour and particle size distribution of defects considered in the method,it is also not constrained by the shape of nets on the layout,which provides a more accurate basis for optimizing layout.

Key words: layout optimization;image processing;expansion algorithm;critical area

CLC Number:

TN41

NING Pan,WANG Junping,ZHANG Guangyan,CAO Honghua,LI Jin,LI Changjiang,LI Bo. Method for Optimizing Layout Based on Image Processing[J]., 2013, 26(7): 29-.

References

［1］LUECK M R,REED J D,GREGORY C W,et al.High-density large-area-array interconnects formed by low-temperature cu/sn-cu bonding for three-dimensional integrated circuits［J］.IEEE Transactions on Electron Devices,2012,59(7):1941-1947.

［2］ABBAS Z,YAKUPOV M,OLIVIERI N,et al.Yield optimization for low power current controlled current conveyor［C］.SBCCI 30 IEEE,2012,Aug.-2 Sep.-5.

［3］沙建超,暴洪成.浅谈集成电路国内外技术现状及发展趋势［J］.民营科技,2011(12):52.
［4］张国霞,马佩军,张旭,等.集成电路关键面积研究方法的发展与挑战［J］.微电子学,2009,39(5):704-709.

［5］王俊平,郝跃,任春丽.椭圆缺陷轮廓的关键面积计算模型［C］.郑州:2008年(第十届)中国科协年会,2008.

［6］GAO X,MACCHIARLO L.Track routing optimizing timing and yield:Design Automation Conference (ASP-DAC)［C］.2011 16th Asia and South Pacific,2011:25-28.

［7］Yu-Wei L,Yen-Hung L,Yih-Lang L.Gridless wire ordering,sizing and spacing with critical area minimization［C］.ISQED 2011,2011:14-16.

［8］MULLER D.Optimizing yield in global routing［C］.IEEE/ACM International Conference on Computer-Aided Design,Digest of Technical Papers,ICCAD,2006:480-486.

［9］MINSIK C,HUA X,PURI R,et al.TROY:track router with yield-driven wire planning:design automation conference［C］.44th ACM/IEEE,2007:4-8.

［10］张俊明.成品率估计与提升技术研究［D］.西安:西安电子科技大学,2009.

［11］FONG L C,CHIN A.Failure analysis on plasma charging induced damage due to effect of circuit layout device structure marginality［C］.Piscataway,NJ,USA:IEEE.IPFA 2012,2012.

［12］JANSEN S,FLORENCE G,PERRY A,et al.Utilizing design layout information to improve efficiency of SEM defect review sampling［C］.Cambridge,MA,United States:ASMC Proceedings,2008.

［13］赵天绪,段旭朝,马佩军,等.基于关键面积的冗余集成电路成品率分析［J］.半导体学报,2003,24(5):544-549.

［14］马佩军.集成电路功能成品率仿真与优化技术研究［D］.西安:西安电子科技大学,2000.

［15］陆勇.集成电路功能成品率模型及参数提取方法的研究［D］.西安:西安电子科技大学,2002.

［16］王俊平.集成电路功能成品率的估计模型研究［D］.西安:西安电子科技大学,2005.

［17］王俊平,郝跃,张卓奎,等.椭圆缺陷轮廓的成品率估计［J］.西安电子科技大学学报:自然科学版,2006,33(3):433-437.

［18］MINSIK C,HUA X,PURI R,et al.Track routing and optimization for yield［J］.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2008,27(5):872-882.

［19］WANG Junping,REN Guangliang,NI Hao.WCA with size and space distribution of real defects for 65-90 nm［C］.2008 2nd International Conference on Anti-Counterfeiting,Security And Processes,2008:181-184.

［20］王俊平,郝跃.65~90 nm技术节点的WCA模型和提取算法［J］.物理学报,2009(6):4267-4273.

［21］王强,王俊平,任春丽.基于线性规划的关键面积缩小算法研究［J］.电子科技,2008,21(10):1-4.

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Method for Optimizing Layout Based on Image Processing

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