锁相环电源噪声激起的抖动灵敏度研究

Abstract

Abstract:

PLL is noise-sensitive devices and power-supply noise is the largest source of interference.For a high system performance,reducing power-supply noise is the only choice for most engineers.The concept is presented in the paper that power-supply noise induced jitter in different frequencies is different and that reducing noise alone may lead to over-design or failure.A SPICE model of PLL is built and self-developed software is used to illustrate the concept of jitter sensitivity.

Key words: PLL;power-supply noise;SPICE;jitter sensitivity

CLC Number:

TN911.6

Cite this article

CHANG Bo-Hao, LIN Yong-Jia. Power-supply Noise Induced Jitter Sensitivity in PLL[J]., 2014, 27(2): 62-.

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URL: https://journal.xidian.edu.cn/dzkj/EN/

https://journal.xidian.edu.cn/dzkj/EN/Y2014/V27/I2/62

References

［1］ZHAO Wenhu,WANG Zhigong,ZHU En.A 3.125-Gb/s CMOS word alignment demultiplexer for serial data communications［C］.Paris:The 29th European Solid-State Circuits Conference,2003.

［2］CHANG K,LEE H,CHUN J H,et al.A 16Gb/s/link,64GB/s bidirectional asymmetric memory interface cell［C］.in Symposium on VLSI Circuits Digest of Technical Papers,2008:126-127.

［4］Synosys Inc.HSPICE user guide:simulation and analysis［M］.CA USA:Version-C,2009.

［5］ARAKALI A,GONDI S,HANUMOLU S P K.A 0.5-to-2.5GHz supply-regulated PLL with noise sensitivity of -28DB［C］.Berlin:IEEE 2008 Custom Intergrated Circuits Conference (CICC),2008.

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