Abstract:

A programmable high speed integer divider based on the 65 nm CMOS (Complementary Metal Oxide Semiconductor,CMOS) technology is designed according to the specifications of the phase locked loop in the IEEE 802.3ae XAUI protocol.A D-flip flow trigger is used to percale the output clock of voltage control oscillator,and the divider building blocks (the 4/5 dual modulus percale and 2- and 5-bit programmable counters) are capable of operating within the division ratio of 8~131.Simulation results show that the maximum operating frequency of the proposed divider is 4.375 GHz,and the current is less than 0.4 mA at 1 V supply voltage.

Key words: divider;high speed;low power;CMOS