Abstract:

A new method of three-phase-locked loop controller base on Xilinx System Generator (SG) is presented,which facilitates simulation debugging in Simulink while saving the need for complex code writing.According to the principle of three-phase power phase-locked loop (PLL),the SG Model of PLL is built.The HDL code of this model is generated by SG automatically and imported into an ISE project.The Feasibility of this method of PLL is proved by downloading the bit file generated by ISE into FPGA.

Key words: FPGA;automatic code generation;PLL;system generator