›› 2016, Vol. 29 ›› Issue (6): 19-.
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WANG Shumin,CUI Xiaoping
Online:
Published:
Abstract:
Aiming at the problem that the hardware implementation of the BCD code decimal addition requires the processing of invalid code, a new decimal adder based on the parallel prefix structure is designed. The proposed decimal adder based on the algorithm of adding six to each BCD digit of one operand prior to performing binary addition and then subtract six again if a carryout of the digit is not occur. The parallelism of circuit operation is increased by taking the advantage of parallel prefix structure. The designed decimal adder have been realized by Verilog HDL and synthesized by Design Compiler, the delay of decimal adder in 32 bit, 64 bit and 128 bit is 0.56 ns, 0.61 ns and 0.71 ns; the area is 1310 μm2, 2681 μm2 and 5485 μm2 .
Key words: decimal addition, parallel prefix structure, carry select adder of subtraction 6
CLC Number:
WANG Shumin,CUI Xiaoping. Design of Decimal Adder Based on Parallel Prefix Structure[J]., 2016, 29(6): 19-.
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https://journal.xidian.edu.cn/dzkj/EN/Y2016/V29/I6/19
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