Abstract: Aiming at the multi-mode requirement of DFT pre-coding in LTE uplink, a DFT hardware implementation scheme based on ASIC was proposed. Radix-4/2/5/3 butterfly unit based on WFTA algorithm was used to achieve 35 different lengths of DFT operation. The two-dimensional cache structure was utilized to achieve pipeline processing of butterfly unit. The chip occupied 0.87mm2 core area and 12.5mW power consumption at 200 MHz frequency and SMIC 40 nm technology. The simulation and synthesis results showed that the DFT hardware accelerator had the advantages of high computing speed and less storage resources, which was suitable for LTE engineering applications.

Key words: LTE uplink , DFT, WFTA algorithm, ASIC, butterfly unit, pipeline processing