Abstract: Aiming at the problems of traditional embedded processors such as high power consumption, the hardware acceleration of the software was proposed to improve the computing performance of the image processing system program. In this paper, With the usage of Vivado HLS, a high-level synthesis tool, OpenCV and C++ algorithms were translated into RTL hardware through hardware-software co-design. The design results showed that the scheme effectively improved the computing performance of the system and shorten the hardware development cycle.

Key words: Vivado HLS, openCV, FPGA, mage coordinates, hardware acceleration, RTL hardware