非规则LDPC码编码器的FPGA实现

Abstract

Abstract:

This article implements the rules of a kind of low density parity check code (LDPC) on hardware.Under the condition of certain constraints,a check matrix structure is used to reduce the encoding complexity of LDPC codes.The design principle,structure and basic composition of the encoder are given.All module functions in the entire coding process are achieved using FPGA Verilog hardware description language on the Quartus 9.0 software platform and the ALTERA Cyclone series EP1C6Q240C8N as the hardware platform.Matlab simulation verifies the correctness of the encoding results.This encoding scheme can be flexibly applied to systems of different code lengths.

Key words: &pi, rotation of LDPC codes;irregular;FPGA;Verilog

CLC Number:

TN762

XU Wei,YU Pai. Implementation of Irregular LDPC Code Encoder FPGA[J]., 2014, 27(5): 51-.

Implementation of Irregular LDPC Code Encoder FPGA

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