Abstract:

This paper introduces the conception of DFT(Design For Testability) technology and test coverage with a PLC(Power Line Communication) chip as an example.An obvious adjustment has been made based on test coverage and power of the design.These optimization methods have greatly improved test coverage,reduced the cost and power consumption,and improved DFT quality.Finally,the design went on to mass production successfully.

Key words: design for testability(DFT);low power design;test coverage