Abstract:

The FPGA system analyzed in this paper has the digital circuit as its core.It is composed of the digital signal generator,low pass filter,adder,pseudo random signal generator and digital signal analysis circuit.The system scheme is compared and the circuit and software are analyzed and designed.To reduce the data rate error and pseudo random code error,eye and eye amplitude were measured.Test results show that error values are within the allowable range.

Key words: manchester code;digital phase-locked loop;synchronized clock signal;eye diagram