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A Novel Second Order Phase Locked Loop with Adaptive Adjusted Bandwidth
ZHAO Lei,SHI Lei,ZHU Congying,YAO Bo
Electronic Science and Technology    2019, 32 (1): 1-4.   DOI: 10.16180/j.cnki.issn1007-7820.2019.01.001
Abstract   (391 HTML19 PDF(pc) (1392KB)(52)  

The large acquisition bandwidth presents a significant challenge to traditional second-order phase locked loops. On the basis of the contradiction of larger acquisition bandwidth and noise reduction capabilities, a novel second-order PLL which was coupled with a nonlinear element, was introduced in this paper. The loop noise bandwidth was adaptively adjusted by the nonlinear element. The frequency error was reduced more quickly with a larger bandwidth when the frequency error was large. By contrast, the noise was suppressed with a smaller bandwidth to improve the tracking accuracy when the frequency error was reduced due to the control effect of the loop. The simulation results indicated that the tracking speed of the proposed nonlinear second order PLL was significantly increased and the acquisition bandwidth was increased from 4 kHz to 18.8 kHz.


Figure 5. Comparison of PLL phase error performance under 1 kHz frequency offset
(a)The phase error under 1kHz frequency deviation(b)The phase error after 2.95 ms
Extracts from the Article
测试条件2 实验中设置环路输入角频率为ωo-=2π×1.99e5 rad/s,则此时环路的输入输出频偏为1 kHz, 输入噪声为ni=0.01×sin(1e4×t),环路输入输出相位误差如图5所示。
由图5可以看出,在输入输出频偏为1 kHz时,NPLL1和NPLL2依然比传统锁相环路更快实现锁定,且NPLL1相位误差抖动幅度与传统锁相环路相位误差抖动幅度相当,说明这种新型锁相环路在大捕获带宽下的适应性较强。
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