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A Novel Second Order Phase Locked Loop with Adaptive Adjusted Bandwidth
ZHAO Lei,SHI Lei,ZHU Congying,YAO Bo
Electronic Science and Technology    2019, 32 (1): 1-4.   DOI: 10.16180/j.cnki.issn1007-7820.2019.01.001
Abstract   (391 HTML19 PDF(pc) (1392KB)(52)  

The large acquisition bandwidth presents a significant challenge to traditional second-order phase locked loops. On the basis of the contradiction of larger acquisition bandwidth and noise reduction capabilities, a novel second-order PLL which was coupled with a nonlinear element, was introduced in this paper. The loop noise bandwidth was adaptively adjusted by the nonlinear element. The frequency error was reduced more quickly with a larger bandwidth when the frequency error was large. By contrast, the noise was suppressed with a smaller bandwidth to improve the tracking accuracy when the frequency error was reduced due to the control effect of the loop. The simulation results indicated that the tracking speed of the proposed nonlinear second order PLL was significantly increased and the acquisition bandwidth was increased from 4 kHz to 18.8 kHz.


Figure 6. Comparison of PLL phase error performance under 4 kHz frequency offset
(a)The phase error under 4 kHz frequency deviation(b)The phase error after 2.95 ms
Extracts from the Article
测试条件3 实验中将环路的输入角频率设置为ωo=2π×1.96e5 rad/s,则此时环路输入输出频偏为4 kHz, 输入噪声为ni=0.01×sin(1e4×t),环路输入输出相位误差如图6所示。
由图6可知,当环路输入输出频偏为4 kHz时,传统锁相环出现了一次跳周现象,而新型锁相环路NPLL1和NPLL2依然能够实现锁定。因此新型锁相环对大捕获带宽的适应性强于传统锁相环路。
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