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A Novel Second Order Phase Locked Loop with Adaptive Adjusted Bandwidth
ZHAO Lei,SHI Lei,ZHU Congying,YAO Bo
Electronic Science and Technology    2019, 32 (1): 1-4.   DOI: 10.16180/j.cnki.issn1007-7820.2019.01.001
Abstract   (391 HTML19 PDF(pc) (1392KB)(52)  

The large acquisition bandwidth presents a significant challenge to traditional second-order phase locked loops. On the basis of the contradiction of larger acquisition bandwidth and noise reduction capabilities, a novel second-order PLL which was coupled with a nonlinear element, was introduced in this paper. The loop noise bandwidth was adaptively adjusted by the nonlinear element. The frequency error was reduced more quickly with a larger bandwidth when the frequency error was large. By contrast, the noise was suppressed with a smaller bandwidth to improve the tracking accuracy when the frequency error was reduced due to the control effect of the loop. The simulation results indicated that the tracking speed of the proposed nonlinear second order PLL was significantly increased and the acquisition bandwidth was increased from 4 kHz to 18.8 kHz.


Figure 7. The phase error in different frequency deviation
Extracts from the Article
最后对两种新型耦合非线性环节的二阶锁相环路的最大捕获带宽与传统锁相环路进行了比较,如图7 所示。当输入输出频偏从4 kHz增大到6 kHz进而增大到6.2 kHz时,NPLL1依然能够实现锁定(如图7中NPLL1箭头所指线条所示)。但是当输入输出频偏继续增大时环路出现了一次跳周现象, 所以NPLL1的捕获带宽相比传统锁相环路从4 kHz增大到了6.2 kHz。当输入输出频偏增大到18.8 kHz时,NPLL2依然能够实现锁定(如图7中NPLL2箭头所指线条所示)。当输入输出频偏继续增大时环路出现一次跳周现象,NPLL2的捕获带框从4 kHz增大到了18.8 kHz。
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