一种高性能的全数字锁相环设计方案

doi:10.19665/j.issn1001-2400.2019.01.018

西安电子科技大学学报 ›› 2019, Vol. 46 ›› Issue (1): 112-116.doi: 10.19665/j.issn1001-2400.2019.01.018

一种高性能的全数字锁相环设计方案

屈八一¹,程腾¹,俞东松¹,李智奇²,周渭²,李珊珊¹,刘立东¹

^1. 长安大学信息工程学院陕西西安 710064
^2. 西安电子科技大学机电工程学院,陕西西安 710071

收稿日期:2018-08-30 出版日期:2019-02-20 发布日期:2019-03-05
作者简介:屈八一(1981-),男,副教授,E-mail: 404182049@qq.com.
基金资助:
国家自然科学基金(11773022);国家自然科学基金(11873039);国家自然科学基金(61701043);中央高校基本科研业务费专项资金(301824171002);长安大学大学生创新创业训练计划(201810710050)

Design scheme for an all-digital phase locked loop with a high performance

QU Bayi¹,CHENG Teng¹,YU Dongsong¹,LI Zhiqi²,ZHOU Wei²,LI Shanshan¹,LIU Lidong¹

^1. School of Information Engineering, Chang’an University, Xi’an 710064;
^2. School of Mechano-electronic Engineering, Xidian Univ., Xi’an 710071, China;

Received:2018-08-30 Online:2019-02-20 Published:2019-03-05

摘要/Abstract

摘要：

针对实现参考频率和输出的频率近似相等或者近似成整数倍关系时遇到的锁相环设计方案复杂以及高性能的模拟锁相环不适宜于集成化问题,设计了主要由模数转换器、全数字式鉴相器、数字式低通滤波器和数控振荡器等构成的全数字式锁相环。主要利用模数转换器在动态量采集时具有的边沿效应从其采集的大量数据中选择出精度更高的数据用于后级的全数字式鉴相,实现了一种全数字式锁相环。实验结果表明了该方案的正确性及其具有锁定精度高和环路的本底噪声低等特性。

关键词: 数字锁相环, 边沿效应, 全数字式鉴相器, 数控振荡器

Abstract:

Aiming at the fact that a complex scheme is needed when the two frequencies in the phase locked loop are close to each other or have an approximate integer multiple relationship and the traditional analog phase locked loop is unsuitable for integration and on chip implementation, an all-digital phase locked loop is proposed, which is mainly composed of analog to digital converters, an all-digital phase detector, a digital low pass filter and a digitally controlled oscillator. The analog to digital converters’ quantization errors have been greatly suppressed by using the clock cursor effect and digital edge effect and an all-digital phase locked loop with a high performance is achieved. Experiment indicates the correctness of the design scheme and shows that the proposed loop has characteristics of high precision and low noise.

Key words: digital phase locked loop, edge effect, all-digital phase detector, digitally controlled oscillator

中图分类号:

TN911.8

屈八一,程腾,俞东松,李智奇,周渭,李珊珊,刘立东. 一种高性能的全数字锁相环设计方案[J]. 西安电子科技大学学报, 2019, 46(1): 112-116.

QU Bayi,CHENG Teng,YU Dongsong,LI Zhiqi,ZHOU Wei,LI Shanshan,LIU Lidong. Design scheme for an all-digital phase locked loop with a high performance[J]. Journal of Xidian University, 2019, 46(1): 112-116.

图/表 4

参考文献 11

[1]	JANG T, JEONG S, JEON D , et al. A Noise Reconfigurable All-digital Phase-locked Loop Using a Switched Capacitor Based Frequency-locked Loop and a Noise Detector[J]. IEEE Journal of Solid-State Circuits, 2018,53(1):50-65. doi: 10.1109/JSSC.2017.2776313
[2]	VILA VALLS J, CLOSAS P, NAVARRO M , et al. Are PLLs Dead? A Tutorial on Kalman Filter-based Techniques for Digital Carrier Synchronization[J]. IEEE Aerospace and Electronic Systems Magazine, 2017,32(7):28-45. doi: 10.1109/MAES.2017.150260
[3]	JANG S C, KIM S W, CHU S H , et al. An Optimum Loop Gain Tracking All-digital PLL Using Autocorrelation of Bang-Bang Phase-frequency Detection[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2015,62(9):836-840. doi: 10.1109/TCSII.2015.2435691
[4]	NAMGOONG W . A Modified Proportional-Integral Loop Filter to Suppress DCO Noise in Digital PLL[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2018,65(8):974-978. doi: 10.1109/TCSII.2018.2794821
[5]	屈八一, 宋焕生, 周渭 , 等. 一种新型不同频直接鉴相的锁相环[J]. 西安电子科技大学学报, 2014,42(2):172-177. doi: 10.3969/j.issn.1001-2400.2014.02.028
	QU Bayi, SONG Huansheng, ZHOU Wei , et al. Novel Phase-locked Loop with Direct Phase Detection for Two Frequency Different Signals[J]. Journal of Xidian University, 2014,41(2):172-177. doi: 10.3969/j.issn.1001-2400.2014.02.028
[6]	RYU S, YEO H, LEE Y , et al. A 9.2 GHz Digital Phase-locked Loop with Peaking-free Transfer Function[J]. IEEE Journal of Solid-State Circuits, 2014,49(8):1773-1784. doi: 10.1109/JSSC.2014.2312412
[7]	GOLESTAN S, GUERRERO J M, VASQUEZ J C . Steady-state Linear Kalman Filter-based PLLs for Power Applications: a Second Look[J]. IEEE Transactions on Industrial Electronics, 2018,65(12):9785-9800. doi: 10.1109/TIE.2018.2818665
[8]	LIN J M, YANG C Y . A Fast-locking All-digital Phase-locked Loop with Dynamic Loop Bandwidth Adjustment[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2015,62(10):2411-2422. doi: 10.1109/TCSI.2015.2477575
[9]	偶晓娟, 周渭, 易韦韦 , 等. 精密频率测量边沿效应的特性分析[J]. 西安电子科技大学学报, 2016,43(3):144-148. doi: 10.3969/j.issn.1001-2400.2016.03.025
	OU Xiaojuan, ZHOU Wei, YI Weiwei , et al. Characteristic Analysis of the Border Effect in Precision Frequency Measurement[J]. Journal of Xidian University, 2016,43(3):144-148. doi: 10.3969/j.issn.1001-2400.2016.03.025
[10]	许龙飞, 罗丹, 周渭 , 等. 一种全面响应时间的频率稳定度测量[J]. 西安电子科技大学学报, 2018,45(1):72-75. doi: 10.3969/j.issn.1001-2400.2018.01.013
	XU Longfei, LUO Dan, ZHOU Wei , et al. Method of a Comprehensive Response Time of Frequency Stability[J]. Journal of Xidian University, 2018,45(1):72-75. doi: 10.3969/j.issn.1001-2400.2018.01.013
[11]	BAI L N, LIU H D, ZHOU W , et al. ADC Border Effect and Suppression of Quantization Error in the Digital Dynamic Measurement[J]. Chinese Physical B, 2017,26(9):090601. doi: 10.1088/1674-1056/26/9/090601

一种高性能的全数字锁相环设计方案

Design scheme for an all-digital phase locked loop with a high performance

RichHTML

PDF (PC)

赞

可视化

摘要/Abstract

引用本文

使用本文

图/表 4

参考文献 11

相关文章 5

Metrics

本文评价

推荐阅读 10

[1]	白丽娜,王一妃,周渭,黄李贝,王远. 从瞬态到全域稳定度的测量方法进步[J]. 西安电子科技大学学报, 2019, 46(3): 8-13.
[2]	偶晓娟;周渭;易韦韦;张晓艳;李晶. 精密频率测量边沿效应的特性分析[J]. 西安电子科技大学学报, 2016, 43(3): 144-148.
[3]	宁小玲;刘忠;罗亚松;龚立;付学志. 一种改进的水声信道载波恢复盲均衡算法[J]. J4, 2012, 39(1): 151-156.
[4]	李建新;郭峰;强刚. 高速突发通信系统中伪码时钟的快速同步[J]. J4, 1998, 25(3): 0-0.
[5]	暂时无作者信息. 单片机控制步长调整的锁相环[J]. J4, 1996, 23(1): 0-0.