52 GHz平衡式二倍频器设计

doi:10.19665/j.issn1001-2400.2019.03.024

西安电子科技大学学报 ›› 2019, Vol. 46 ›› Issue (3): 160-166.doi: 10.19665/j.issn1001-2400.2019.03.024

52 GHz平衡式二倍频器设计

余文敏^1,^2,³,卢煜旻^1,^2,³

^1. 中国科学院上海微系统与信息技术研究所,上海 200050
^2. 中国科学院大学材料与光电研究中心,北京 100049
^3. 中国科学院大学,北京 100049

收稿日期:2018-12-11 出版日期:2019-06-20 发布日期:2019-06-19
作者简介:余文敏(1994-),女,上海微系统与信息技术研究所硕士研究生,E-mail: yuwm0815@163.com.
基金资助:
中组部青年千人计划(Y5SQRB1001)

Design of a 52 GHz balanced frequency doubler

YU Wenmin^1,^2,³,LU Yumin^1,^2,³

^1. Shanghai Institute of Microsystem and Information Technology of the Chinese Academy of Science, Shanghai 200050
^2. Center of Materials Science and Optoelectronics Engineering, University of the Chinese Academy of Sciences, Beijing 100049
^3. University of Chinese Academy of Science, Beijing 100049

Received:2018-12-11 Online:2019-06-20 Published:2019-06-19

摘要/Abstract

摘要：

为获得高频信号源,采用0.13 μm 的锗硅双极结型晶体管和互补金属氧化物半导体工艺设计并实现了一种高效率和高基频抑制的52 GHz平衡式二倍频器。二倍频器采用了差分共射-共基结构,且在输入端采用了一个单端转差分的巴伦,并利用二次谐波反射器减小反馈到输入的二次谐波对输出信号的影响,有效地提高了二次谐波输出功率。探针台测试结果表明,巴伦在2026.5 GHz范围内的插入损耗约为1 dB,且当二倍频器输入26 GHz信号,功率为0.5 dBm时,输出的52 GHz信号功率达到2.3 dBm,相应的基频抑制达到34 dBc,直流功耗约为21.8 mW,相应的功率附加效率为2.5%。这种二倍频器在达到高输出功率和高基波抑制的同时保持了较低的功耗。

关键词: 二倍频器, 锗硅, 异质结双极晶体管, 二次谐波反射器

Abstract:

In order to generate a high frequency signal source, a 52 GHz balanced frequency doubler with high efficiency and good fundamental rejection is designed. The doubler is fabricated in a 0.13 μm SiGe Bipolar junction transistor by the Complementary Metal Oxide Semiconductor (BiCMOS) technology. A balun is used to split the single-ended signal into differential signals. A second harmonic reflector reduces the effect of the feedback signal of the second harmonic on the output signal and improves the output power. The measurement results based on the probe station demonstrate that the insertion loss of the balun is about 1 dB from 20 GHz to 26.5 GHz. With an input power of 0.5 dBm, the doubler delivers an output second harmonic power of 2.3 dBm with 34 dBc of fundamental rejection. The doubler consumes a dc power of about 21.8 mW with the corresponding power-added efficiency (PAE) of 2.5%.

Key words: frequency doubler, SiGe, heterojunction bipolar transistor, second harmonic reflector

中图分类号:

TN771

余文敏,卢煜旻. 52 GHz平衡式二倍频器设计[J]. 西安电子科技大学学报, 2019, 46(3): 160-166.

YU Wenmin,LU Yumin. Design of a 52 GHz balanced frequency doubler[J]. Journal of Xidian University, 2019, 46(3): 160-166.

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参考文献 12

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文献	工艺/f_T(GHz)	f_out/GHz	P_in /dBm	P_out@2f₀ /dBm	CG/dB	P_dc/mW	FR/dBc	芯片面积 /mm²
文献[9]	0.1μm GaAs pHEMT^#	58.6	6.0	15.20	9.20	146.0	35.0	(0.77)
文献[10]^*	0.13μm CMOS	54.2	-4.0	-4.45	-0.45	9.0	49.2	1.24×0.75(0.924)
文献[11]	90nm CMOS	46.0	0	-1.60	-1.60	11.5	25.0	0.9×0.7(0.630)
文献[12]	0.13μm SiGe/350	62.0	-4.0	-19.00	-15.00	23.5	42.0	0.86×0.635 (0.550)
文中	0.13μm SiGe/103	52.0	0.5	2.30	1.80	21.8	34.0	0.61×0.6 (0.366)^**

52 GHz平衡式二倍频器设计

Design of a 52 GHz balanced frequency doubler

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