电源门控技术中的电压噪声优化方案

doi:10.19665/j.issn1001-2400.2019.05.007

西安电子科技大学学报 ›› 2019, Vol. 46 ›› Issue (5): 48-54.doi: 10.19665/j.issn1001-2400.2019.05.007

电源门控技术中的电压噪声优化方案

王磊磊^1,^2,³,王璐¹

^1. 上海科技大学信息科学与技术学院,上海 201210
^2. 中国科学院上海微系统与信息技术研究所,上海 200050
^3. 中国科学院大学电子电气与通信工程学院,北京 100049

收稿日期:2019-04-20 出版日期:2019-10-20 发布日期:2019-10-30
作者简介:王磊磊(1990—),男,中国科学院上海微系统与信息技术研究所博士研究生,E-mail:wangll@shanghaitech.edu.cn.
基金资助:
国家自然科学基金(61401276)

Optimization of the voltage noise induced by the power gating technique

WANG Leilei^1,^2,³,WANG Lu¹

^1. School of Information Science and Technology, ShanghaiTech University, Shanghai 201210, China
^2. Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050, China
^3. School of Electronic, Electrical and Communication Engineering, University of Chinese Academy of Sciences, Beijing 100049, China

Received:2019-04-20 Online:2019-10-20 Published:2019-10-30

摘要/Abstract

摘要：

由于电压噪声严重威胁着芯片功能的正常运行,因此提出了一种系统层面的电路模块开启序列优化方案,以减小使用电源门控技术的电路模块在开启时产生的电压噪声。通过建立和求解混合整数线性规划问题,获得最优的多电路模块在规定完成时间内接入电网的顺序及时间间隔,从而使得引入的电压噪声能最大程度地减小。实验结果表明,电源门控技术开启方案能减小引入的电压噪声达30%以上,并且获得了开启操作的完成时间与引入的电压噪声之间的权衡关系。因此,这种开启序列优化方案能在不同的规定完成时间内,大幅度地减小电源门控技术引入的电压噪声。

关键词: 供电网络, 电压噪声, 电源门控技术, 开启序列, 混合整数线性规划

Abstract:

Since voltage noise could threaten the correct execution of the chip function, in this paper a system-level power gating sequence is proposed to reduce the induced voltage noise by turning on circuit modules with power gating. By establishing and solving the mixed integer linear programming problem, we can obtain the optimal order and time interval of multi-circuit modules to connect the power grid within the specified time constrain, so that the introduced voltage noise can be minimized. Experimental results show that our power gating schedules can reduce the introduced voltage noise by over 30%, and we also get the trade-off between the time constrain and the introduced voltage noise. Hence, our power gating sequence could significantly reduce the induced power noise under different time constrains.

Key words: power grid, voltage noise, power gating, turn-on sequence, mixed integer linear programming

中图分类号:

TN47

王磊磊,王璐. 电源门控技术中的电压噪声优化方案[J]. 西安电子科技大学学报, 2019, 46(5): 48-54.

WANG Leilei,WANG Lu. Optimization of the voltage noise induced by the power gating technique[J]. Journal of Xidian University, 2019, 46(5): 48-54.

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时间约束	4
方法种类	方法1	方法2	*	方法1	方法2	*	方法1	方法2	*	方法1	方法2	*
最大噪声	0.505	0.505	0.494	0.323	0.324	0.205	0.212	0.207	0.132	0.213	0.256	0.132
减小比例	2.1%	2.1%	-	36.5%	36.7%	-	37.6%	36.2%	-	38.0%	48.3%	-

电源门控技术中的电压噪声优化方案

Optimization of the voltage noise induced by the power gating technique

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