RM逻辑伪装门的硬件混淆设计

doi:10.19665/j.issn1001-2400.2020.02.018

西安电子科技大学学报 ›› 2020, Vol. 47 ›› Issue (2): 135-141.doi: 10.19665/j.issn1001-2400.2020.02.018

• • 上一篇

RM逻辑伪装门的硬件混淆设计

吴秋丰¹,张跃军¹(),汪鹏君^1,²,张会红¹

1.宁波大学信息科学与工程学院,浙江宁波 315211
2.温州大学电气与电子工程学院,浙江温州 325035

收稿日期:2019-08-29 出版日期:2020-04-20 发布日期:2020-04-26
作者简介:吴秋丰(1993—),男,宁波大学硕士研究生,E-mail:wuqiufeng1006@163.com
基金资助:
国家自然科学基金(61871244);国家自然科学基金(61874078);浙江省自然科学基金(LY18F040002);浙江省大学生新苗人才计划(2019R405072);宁波大学学生科研创新项目(2019SRIP1311);宁波大学王宽诚幸福基金;宁波大学孔爱菊教育基金

Hardware obfuscation design of the RM logical camouflage gate

WU Qiufeng¹,ZHANG Yuejun¹(),WANG Pengjun^1,²,ZHANG Huihong¹

1.School of Information Science and Engineering, Ningbo University, Ningbo 315211, China
2.College of Electrical and Electronic Engineering, Wenzhou University, Wenzhou 325035, China

Received:2019-08-29 Online:2020-04-20 Published:2020-04-26

摘要/Abstract

摘要：

为了提高集成电路抗逆向工程的能力,通过对逻辑混淆技术的研究,提出了一种基于Reed-Muller伪装门的逻辑混淆设计方案。该方案首先在同一版图上采用不同虚拟孔配置实现基本单元异或门/与门逻辑功能,并提取逻辑混淆单元的特征信息制作标准单元库;然后利用随机插入算法将混淆标准单元电路应用于电路网表;最后采用基准电路验证所提方案的有效性。仿真结果显示,Reed-Muller逻辑伪装门比标准单元库的版图相似度提高了14.36%,而较大规模测试电路功耗额外开销仅为2.36%。仿真结果表明,所设计的伪装门可以有效地防御逆向工程,提高了电路的硬件安全。

关键词: 硬件安全, Reed-Muller逻辑, 逻辑混淆, 逆向工程

Abstract:

To improve the ability of the integrated circuit to resist reverse engineering, we study the logic obfuscation technology and propose a logic obfuscation scheme based on the Reed-Muller camouflage gate. First, different virtual hole configurations are adopted to realize XOR/AND logical functions on the same layout, and feature information of the logical obfuscating circuit is extracted to make the standard cell physical library. Then, the obfuscation physical library is applied in the circuit netlist by the random insertion algorithm. Finally, the ISCAS benchmark is used to verify the effectiveness of the proposed scheme. Simulation results reveal that the similarity of the Reed-Muller logic camouflage layout is improved by 14.36%, and that the power consumption overhead is about 2.36% under the larger scale benchmark. Experiment indicates that the designed obfuscation gate can effectively resist reverse engineering and improve the hardware security of the circuit.

Key words: hardware security, Reed-Muller logic, logical obfuscation, reverse engineering

中图分类号:

TN402

吴秋丰,张跃军,汪鹏君,张会红. RM逻辑伪装门的硬件混淆设计[J]. 西安电子科技大学学报, 2020, 47(2): 135-141.

WU Qiufeng,ZHANG Yuejun,WANG Pengjun,ZHANG Huihong. Hardware obfuscation design of the RM logical camouflage gate[J]. Journal of Xidian University, 2020, 47(2): 135-141.

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功能	通孔
功能	真实	虚拟
异或门	1 2 4 5 6 7 8 11	3 9 10 12
与门	1 3 6 8 9 10 11 12	2 4 5 7

文献	混淆方法	工艺/nm	面积开销/%	功耗开销/%	延时开销/%	功耗延时积/%
[10]	电路伪装		66.02	66.89	36.23	24.23
[18]	布尔逻辑锁	台积电65	8.03	28.76	26.56	7.64
[19]	混淆状态机	台积电65	23.00	11.00	19.00	2.09
笔者提出	RM逻辑锁	台积电65	10.73	5.11	47.23	2.41

RM逻辑伪装门的硬件混淆设计

Hardware obfuscation design of the RM logical camouflage gate

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