时钟及面积优化的可配置片上网络路由器

doi:10.19665/j.issn1001-2400.2022.02.015

西安电子科技大学学报 ›› 2022, Vol. 49 ›› Issue (2): 125-134.doi: 10.19665/j.issn1001-2400.2022.02.015

时钟及面积优化的可配置片上网络路由器

胡东伟¹(),尚德龙²,张勇¹(),王力男¹()

1.中国电子科技集团公司第五十四研究所,河北石家庄 050080
2.南京智能技术研究院,江苏南京 211100

收稿日期:2020-08-13 出版日期:2022-04-20 发布日期:2022-05-31
作者简介:胡东伟(1980—),男,高级工程师,E-mail: hudw1980@sina.com;|张勇(1977—),男,工程师,E-mail: yong_1789@163.com;|王力男(1968—),男,研究员,E-mail: wln99@sina.com
基金资助:
国防基础研究计划(HHX20641);国防基础研究计划(HHX21641)

Timing and area optimized re-configurable network-on-chip router

HU Dongwei¹(),SHANG Delong²,ZHANG Yong¹(),WANG Linan¹()

1. 54th Institute of China Electronics Technology Corporation,Shijiazhuang 050080,China
2. Nanjing Institute of Intelligent Technology,Nanjing 211100,China

Received:2020-08-13 Online:2022-04-20 Published:2022-05-31

摘要/Abstract

摘要：

片上网络路由器是实现多核/众核互连的核心电路部件。在介绍同步先进先出缓存器和异步先进先出缓存器的实现电路架构和延迟特点以及片上网络及其路由器架构的基础上,提出了片上网络的时钟优化方案,给出了优化时钟方案下的路由器电路结构,并进行了实现。采用该时钟方案,片上网络路由器间的延迟得以减小。为降低先进先出缓存器的面积开销,进一步提出采用锁存器来实现同步或异步先进先出缓存器,解决了单时钟下的锁存器写问题。更进一步,给出了多个先进先出缓存器的共享实现方案。文章中的方案对开发低功耗嵌入式众核处理器具有直接指导意义。

关键词: 先进先出缓存器, 片上网络, 路由器

Abstract:

The Network-on-Chip Router is the key component of multi/many-core processors.In this paper,firstly the schematic architectures of the synchronous First-Input-First-Output (FIFO) buffer and asynchronous FIFO buffer are reviewed with their latencies addressed.Then the architectures of the Network-on-Chip (NoC) and its router are introduced.With the previous foundations,an optimized clock tree distribution scheme,as well as the NoC router implementation under this clock tree distribution scheme,are proposed.With this novel clock tree optimization,the latency of the NoC is greatly reduced.In addition,in order to decrease the area of the register based FIFO,the latch based FIFO is proposed.Single tick latch writing is ensured.And sharing multiple FIFOs is proposed.The proposed techniques are especially useful for embedded low-power many-core processors.

Key words: first-input-first-output, network-on-chip, router

中图分类号:

胡东伟,尚德龙,张勇,王力男. 时钟及面积优化的可配置片上网络路由器[J]. 西安电子科技大学学报, 2022, 49(2): 125-134.

HU Dongwei,SHANG Delong,ZHANG Yong,WANG Linan. Timing and area optimized re-configurable network-on-chip router[J]. Journal of Xidian University, 2022, 49(2): 125-134.

图/表 15

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参考文献 17

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结构	组合逻辑	时序逻辑	总面积
图5(b)结构	10 466.3	20 728.5	31 194.8
图8结构	8 070.3	21 399.8	29 470.1

结构	组合逻辑	时序逻辑(含锁存器)	总面积
图5(b)寄存器	10 466.3	20 728.5	31 194.8
图5(b)锁存器	9 273.9	13 117.1	22 391.0
图8寄存器	8 070.3	21 399.8	29 470.1
图8锁存器	8 194.3	14 110.0	22 304.3

结构	组合逻辑	时序逻辑(含锁存器)	总面积
不共享	8 194.3	14 110.0	22 304.3
共享	21 295.3	14 162.7	35 457.9

时钟及面积优化的可配置片上网络路由器

Timing and area optimized re-configurable network-on-chip router

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