关键词: 忆阻器阵列, 存算一体架构, 单粒子翻转, BCH码, 多比特纠错

Abstract:

The memristor compute-in-memory(CIM) architecture,as a new technique that integrates storage and computing,can effectively address the problems of a limited data transmission rate,frequent data migration,increased transmission power consumption and delay caused by the separation of storage and computation in traditional von Neumann architecture data error correction,thereby improving the satellite-borne electronic system reliability and stability.However,existing CIM error correction techniques can only correct the single-bit data error and fail to handle continuous multi-bit error detection and correction.Thus,this paper proposes a memristor CIM-based BCH multi-bit error correction method.First,we convert the traditional encoding and decoding operations such as modulo,multiply add and forward search into matrix operations to simplify the calculation process and reduce resource overhead.Second,we construct finite field multiply-accumulate and multiply calculation units separately,and based on the operational requirements and data characteristics of each stage of the BCH algorithm,parallel processing is utilized to adaptively select the corresponding computing cores to further improve the operational efficiency.Finally,the proposed method is verified on the Calculator and MNSIM simulation platforms of Cadence.Experimental results show that the proposed method achieves efficient and stable multi-bit error correction,that the data throughput is 8.8 MHz,that the operating power consumption is less than 40mW,and that the area overhead is 3×105 um² in 65 nm.Specifically,compared to FPGA and IMPLY architectures,the computational efficiency has increased by 7× and 400×,respectively.

Key words: memristor cross-bar, compute-in-memory architecture, single-event upset, BCH code, multi-bit correction