J4 ›› 2010, Vol. 37 ›› Issue (1): 158-162.doi: 10.3969/j.issn.1001-2400.2010.01.028

• 研究论文 • 上一篇    下一篇

图像混合插值缩放IP核的VLSI设计

葛晨阳;郑南宁;任鹏举   

  1. (西安交通大学 人工智能与机器人研究所,陕西 西安  710049)
  • 收稿日期:2008-10-08 出版日期:2010-02-20 发布日期:2010-03-29
  • 通讯作者: 葛晨阳
  • 作者简介:葛晨阳(1977-),男,西安交通大学博士研究生,E-mail: cyge@mail.xjtu.edu.cn.
  • 基金资助:

    国家高技术研究发展计划(863)资助项目(2009AA01Z307)

VLSI design of the image scaling IP core with the mixed interpolation algorithm

GE Chen-yang;ZHENG Nan-ning;REN Peng-ju   

  1. (Inst. of Artificial Intelligence and Robotics, Xi'an Jiaotong Univ., Xi'an  710049, China)
  • Received:2008-10-08 Online:2010-02-20 Published:2010-03-29
  • Contact: GE Chen-yang

摘要:

为解决不同的输入视频源在固定分辨率的平板显示器件上无损显示问题,提出一种基于双线性和双三次混合插值的图像缩放算法及其硬件实现方法.基于混合插值算法,完成图像缩放IP核的VLSI设计.该IP核支持多种格式的输入源,无需外部存储器实现高精度的缩放功能,并作为嵌入式IP核在数字视频处理芯片DTV100B中进行功能验证正确.混合插值方法在保持图像细节和清晰度方面优于双线性插值,而在内部存储资源开支上不到双三次插值的1/2.

关键词: 图像缩放, 双线性, 双三次, IP核, 超大规模集成电路

Abstract:

In order to solve the problem of various input video sources displaying in flat panel display devices which have the fixed resolution without any distortion, an algorithm for image scaling based on mixed interpolation by bilinear and bicubic is proposed, and its corresponding hardware implementation is also presented. The image scaling IP core is designed by VLSI based on the mixed interpolation. The input video sources with various formats are supported by it, and the high-precision scaling function without external storage is implemented. As an embedded IP core, the image scaling core is verified to be correct in function in the digital video processing chip DTV100B. The mixed interpolation method is superior in image detail and definition preserving to bilinear interpolation, and its expense of internal memory resources is less than half that of bicubic interpolation.

Key words: image scaling, bilinear, bicubic, IP core, VLSI