256MHz采样71dB动态范围连续时间ΣΔADC设计

doi:10.3969/j.issn.1001-2400.2015.01.002

J4 ›› 2015, Vol. 42 ›› Issue (1): 10-15.doi: 10.3969/j.issn.1001-2400.2015.01.002

256MHz采样71dB动态范围连续时间ΣΔADC设计

杨银堂¹;袁俊¹;张钊锋²

(1. 西安电子科技大学宽禁带半导体材料与器件教育部重点实验室，陕西西安 710071;
2. 中国科学院上海高等研究院信息科学与技术研究部，上海 201203)

收稿日期:2013-10-27 出版日期:2015-02-20 发布日期:2015-04-14
通讯作者: 杨银堂
作者简介:杨银堂(1962-)，男，教授， E-mail: ytyang@xidian.edu.cn．
基金资助:
国家重大专项资助项目(2010ZX03006-003-02)

Continuous time ΣΔADC design with 256MHz sampling and 71dB DR

YANG Yintang¹;YUAN Jun¹;ZHANG Zhaofeng²

(1. Ministry of Education Key Lab. of Wide Band-Gap Semiconductor Materials and Devices, Xidian Univ., Xi'an 710071, China;
2. Shanghai Advanced Research Institute, Chinese Academy of Sciences, Shanghai 201203, China)

Received:2013-10-27 Online:2015-02-20 Published:2015-04-14
Contact: YANG Yintang

摘要/Abstract

摘要：

宽带连续时间ΣΔ型数模转换器大量用于无线通信领域．设计了采用三阶4bit连续时间调制器架构．为降低时钟抖动的影响，采用不归零数模转换器反馈脉冲，通过引入半个时钟周期延时来改善环路异步问题，以补偿环路延时对性能的影响．还从电路、算法和版图方面来降低反馈数模转换器失配的影响．由于米勒补偿增加了电容而增大功耗，因此这里采用前馈补偿技术，设计了一款低功耗、高速的运算放大器．最后基于0.13μm工艺，在256MHz采样频率、1.2V电源电压下，在8MHz带宽内信噪失真比达到62.5dB和71dB动态范围，功耗为15mW．

关键词: 模数转换器, 连续时间, ΣΔ型数模转换器

Abstract:

A wide bandwidth continuous time ΣΔADC is widely used in the wireless communication field. A ΣΔADC with the 3 order 4bit modulator is designed with the 256MHz sampling frequency. In order to reduce the clock jitter, the nonreturn-to-zero (NRZ) DAC feedback pulse is used. And the loop asynchronous problem is improved by introducing a half of clock cycle delay. Also how to reduce the effect of the DAC mismatch is discussed. A low voltage, low power, and high speed operational amplifier is designed with feedforward compensation technology. Finally, based on the 0.13μm technology, the SNDR is 62.5dB and DR is 71dB with a 1.2V supply.

Key words: analog to digital converter, continuous time, sigma delta analog to digital converter

中图分类号:

杨银堂;袁俊;张钊锋. 256MHz采样71dB动态范围连续时间ΣΔADC设计[J]. J4, 2015, 42(1): 10-15.

YANG Yintang;YUAN Jun;ZHANG Zhaofeng. Continuous time ΣΔADC design with 256MHz sampling and 71dB DR[J]. J4, 2015, 42(1): 10-15.

参考文献

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256MHz采样71dB动态范围连续时间ΣΔADC设计

Continuous time ΣΔADC design with 256MHz sampling and 71dB DR

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