J4 ›› 2015, Vol. 42 ›› Issue (2): 95-101.doi: 10.3969/j.issn.1001-2400.2015.02.016

• 研究论文 • 上一篇    下一篇



  1. (1. 西安电子科技大学 微电子学院,陕西 西安 710071; 2. 西安邮电大学 电子工程学院,陕西 西安 710121)
  • 收稿日期:2013-11-21 出版日期:2015-04-20 发布日期:2015-04-14
  • 通讯作者: 刘镇弢
  • 作者简介:刘镇弢(1971-),男,西安电子科技大学博士研究生,E-mail: liuzhentao@xupt.edu.cn.
  • 基金资助:
    国家自然科学基金资助项目(61136002, 61272120)

Novel many-core architecture design for real-time image processing

LIU Zhentao1;LI Tao2;HUANG Hucai2;HAN Jungang2;SHEN Xubang1   

  1. (1. School of Microelectronic, Xidian Univ., Xi'an 710071, China; 2. School of Electronic Engineering, Xi'an Univ. of Posts and Telecommunications, Xi'an 710121, China)
  • Received:2013-11-21 Online:2015-04-20 Published:2015-04-14
  • Contact: LIU Zhentao

摘要: 基于数据流模型和硬件可重构技术,提出了一种面向图像处理应用的可重构的多模式众核处理器结构.处理器采用了可扩展的层次化阵列结构,分布式共享存储和带硬件握手的近邻互连,可以分区并发实现多种并行模式,并克服了传统处理器实现数据流计算的低效性;基于VC++开发了集成仿真平台,用于对结构性能和指令性能的仿真验证,并在现场可编程门阵列上实现了包含64个处理单元的所提结构.仿真结果表明,所提结构实现了超过图形处理单元的性能以及接近专用集成电路的数据吞吐量.

关键词: 多模式可重构结构, 数据流, 众核, 并行计算

Abstract: Based on the data-flow model and hardware reconfigurable technology, a polymorphic reconfigurable many-core processor architecture is presented for image processing. It is a scalable hierarchically organized parallel architecture, which is capable of supporting a dynamic mixture of multiple parallel computing models, and overcomes the inefficiency of traditional data-flow implementation by using distributed shared memory and neighbor interconnect architecture with hardware handshaking. From the beginning of the architecture design, based on the VC++, the integrated simulation platform (ISE) is developed for verifying the architecture and the performance of the instruction set. In addition, we also implement the proposed architecture on the FPGA. Experimental results show that the architecture can be used in many image processing applications, and achieve the throughput close to that of the ASIC and the performance better than that of the GPU.

Key words: polymorphic reconfigurable architecture, data-flow, many-core, parallel computin


  • TP391